Abstract: Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass.

Abstract: In one embodiment, a microfluidic sensor device includes microfluidic sensor mounted on and electrically connected a micro lead frame substrate. The microfluidic sensor is molded to form a package body. The package body includes a molded panel portion and, in some embodiments, a mask portion having one or more open channels, sealed channels, and/or a sealed chamber exposing an active surface of the microfluidic sensor. The molded panel portions and mask portions are configured to allow a material to dynamically or statically contact the microfluidic sensor for analysis.

Abstract: Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass.

Abstract: In one embodiment, a microfluidic sensor device includes microfluidic sensor mounted on and electrically connected a micro lead frame substrate. The microfluidic sensor is molded to form a package body. The package body includes a molded panel portion and, in some embodiments, a mask portion having one or more open channels, sealed channels, and/or a sealed chamber exposing an active surface of the microfluidic sensor. The molded panel portions and mask portions are configured to allow a material to dynamically or statically contact the microfluidic sensor for analysis.

Abstract: In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. The semiconductor device comprises a substrate having a conductive pattern formed thereon. In each embodiment of the semiconductor device, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. In certain embodiments, a semiconductor die which is electrically connected to the conductive pattern of the substrate may be fully or partially covered with a film-over-wire. Additionally, in each embodiment of the semiconductor device, the vertically stacked electronic components thereof may be covered with a package body which also partially covers the substrate.

Abstract: A bond pad and a method of making the same for a semiconductor die has a bonding region formed on the bond pad. A test region is formed on the bond pad and is adjacent to the bonding region.

Abstract: In accordance with the present invention, there is provided multiple embodiments of a reduced profile stackable semiconductor package. The semiconductor package comprises a substrate having at least one semiconductor die attached thereto. The semiconductor die is also electrically connected to the substrate by a plurality of conductive wires. A package body defining opposed top and bottom surfaces and a side surface at least partially encapsulates the substrate, the conductive wires and the semiconductor die. The package body is formed such that at least portions of the conductive wires are exposed in the top surface thereof. The package body may include a groove formed in the top surface thereof, with at least portions of the conductive wires being exposed in the groove.