Patents by Inventor Chan Ha Hwang

Chan Ha Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240081722
    Abstract: A method of identifying dementia is disclosed that includes causing a user terminal to display an N-th screen including a plurality of objects. The user terminal may further display an N+1-th screen with the objects rearranged at positions on the N+1-th screen which are different from positions of the objects included in the N-th screen when an N-th selection input of selecting any one from among the objects included in the N-th screen is received. When an N+1-th selection input for selecting any one from among the objects included in the N+1-th screen is received, a third task of determining whether an answer of the N+1-th selection input is correct is performed based on whether the object selected from the N+1-th selection input is the same as at least one object selected from at least one previous selection input including the N-th selection input.
    Type: Application
    Filed: July 7, 2022
    Publication date: March 14, 2024
    Applicant: HAII corp.
    Inventors: Ho Yung KIM, Geon Ha KIM, Bo Hee KIM, Dong Han KIM, Hye Bin HWANG, Chan Yeong PARK, Ji An CHOI, Bo Ri KIM
  • Patent number: 9627348
    Abstract: Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: April 18, 2017
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Dong Su Ryu, Choon Heung Lee, Min Ho Kim, Choong Hoe Kim, Ju Hoon Yoon, Chan Ha Hwang, Yang Gyoo Jung
  • Patent number: 9513254
    Abstract: In one embodiment, a microfluidic sensor device includes microfluidic sensor mounted on and electrically connected a micro lead frame substrate. The microfluidic sensor is molded to form a package body. The package body includes a molded panel portion and, in some embodiments, a mask portion having one or more open channels, sealed channels, and/or a sealed chamber exposing an active surface of the microfluidic sensor. The molded panel portions and mask portions are configured to allow a material to dynamically or statically contact the microfluidic sensor for analysis.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: December 6, 2016
    Assignee: Amkor Technology, Inc.
    Inventors: Hyung II Jeon, Ji Young Chung, Chan Ha Hwang, Byong Jin Kim, Yung Woo Lee, Do Hyun Na, Jae Ung Lee
  • Publication number: 20160049381
    Abstract: Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass.
    Type: Application
    Filed: January 8, 2015
    Publication date: February 18, 2016
    Inventors: Dong Su Ryu, Choon Heung Lee, Min Ho Kim, Choong Hoe Kim, Ju Hoon Yoon, Chan Ha Hwang, Yang Gyoo Jung
  • Publication number: 20150041324
    Abstract: In one embodiment, a microfluidic sensor device includes microfluidic sensor mounted on and electrically connected a micro lead frame substrate. The microfluidic sensor is molded to form a package body. The package body includes a molded panel portion and, in some embodiments, a mask portion having one or more open channels, sealed channels, and/or a sealed chamber exposing an active surface of the microfluidic sensor. The molded panel portions and mask portions are configured to allow a material to dynamically or statically contact the microfluidic sensor for analysis.
    Type: Application
    Filed: August 11, 2014
    Publication date: February 12, 2015
    Inventors: Hyung Il Jeon, Ji Young Chung, Chan Ha Hwang, Byong Jin Kim, Yung Woo Lee, Do Hyun Na, Jae Ung Lee
  • Patent number: 8487420
    Abstract: In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. The semiconductor device comprises a substrate having a conductive pattern formed thereon. In each embodiment of the semiconductor device, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. In certain embodiments, a semiconductor die which is electrically connected to the conductive pattern of the substrate may be fully or partially covered with a film-over-wire. Additionally, in each embodiment of the semiconductor device, the vertically stacked electronic components thereof may be covered with a package body which also partially covers the substrate.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: July 16, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Chan Ha Hwang, Eun Sook Sohn, Ho Choi, Byong Jin Kim, Ji Yeon Yu, Min Woo Lee
  • Patent number: 8198738
    Abstract: A bond pad and a method of making the same for a semiconductor die has a bonding region formed on the bond pad. A test region is formed on the bond pad and is adjacent to the bonding region.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: June 12, 2012
    Assignee: Amkor Technology, Inc.
    Inventors: Chan Ha Hwang, Do Hyun Na, Chang Deok Lee
  • Patent number: 8026589
    Abstract: In accordance with the present invention, there is provided multiple embodiments of a reduced profile stackable semiconductor package. The semiconductor package comprises a substrate having at least one semiconductor die attached thereto. The semiconductor die is also electrically connected to the substrate by a plurality of conductive wires. A package body defining opposed top and bottom surfaces and a side surface at least partially encapsulates the substrate, the conductive wires and the semiconductor die. The package body is formed such that at least portions of the conductive wires are exposed in the top surface thereof. The package body may include a groove formed in the top surface thereof, with at least portions of the conductive wires being exposed in the groove.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: September 27, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Bong Chan Kim, Do Hyung Kim, Chan Ha Hwang, Min Woo Lee, Eun Sook Sohn, Won Joon Kang