Abstract: A light-emitting diode includes a first type semiconductor layer, a stress relief layer disposed on the first type semiconductor layer and including at least one first repeating unit containing a first well layer and a first barrier layer that are alternately stacked, an active layer disposed on the stress relief layer and including at least one second repeating unit containing a second well layer and a second barrier layer that are alternately stacked, a second type semiconductor layer disposed on the active layer, a first electrode electrically connected to the first type semiconductor layer, and a second electrode electrically connected to the second type semiconductor layer. The first well layer is made of an In-containing material. The second well layer is made of an In-containing material. The second barrier layer is formed with multiple sub-layers, each of which is made of an Al-containing material.

Abstract: A data processing apparatus for accessing a plurality of memories is provided. The data processing apparatus includes a function control circuitry and an address generation circuitry. The function control circuitry is utilized to record a first memory address where a first function is implemented after the first function is implemented and to determine which one of the plurality of memories is a target memory according to the first memory address. The address generation circuitry is utilized to output the first memory address to the target memory. In addition, the function control circuitry is configured to determine the target memory in the same processing cycle in which the address generation circuitry is configured to output the first memory address.

Abstract: A data processing apparatus for accessing a plurality of memories is provided. The data processing apparatus includes a function control circuitry and an address generation circuitry. The function control circuitry is utilized to record a first memory address where a first function is implemented after the first function is implemented and to determine which one of the plurality of memories is a target memory according to the first memory address. The address generation circuitry is utilized to output the first memory address to the target memory. In addition, the function control circuitry is configured to determine the target memory in the same processing cycle in which the address generation circuitry is configured to output the first memory address.

Abstract: A method of dynamic data transfer width adjustment is provided. The method includes firstly detects a data size of a transfer data. A data transfer width mode is detected according to a data address of transferring data. The data transfer width mode includes at least one of a word mode, a half-word mode, and a byte mode. According to the data address, the data transfer width mode, and the data size, the data is transferred.

Abstract: A method of dynamic data transfer width adjustment is provided. The method includes firstly detects a data size of a transfer data. A data transfer width mode is detected according to a data address of transferring data. The data transfer width mode includes at least one of a word mode, a half-word mode, and a byte mode. According to the data address, the data transfer width mode, and the data size, the data is transferred.

Abstract: A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

Abstract: A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.