Abstract: A device including a silicon controlled rectifier including an anode and a cathode; at least one first transistor connected between the anode and a gate of the silicon controlled rectifier; and a second transistor including a source connected to one from among the cathode or the anode, and a drain connected to a body of the at least one first transistor.

Abstract: An electrostatic discharge clamp circuit includes a resistor connected between a first node and a second node, a first capacitor connected between the second node and a third node, a second capacitor connected between a fourth node and the third node, a third capacitor connected between a fifth node and the third node, a first inverter providing a power supply voltage or a voltage of the fourth node based on a voltage of the second node, a second inverter providing an output voltage of the first inverter or a voltage of the fifth node based on the voltage of the fourth node, a third inverter configured to provide an output voltage of the second inverter or the ground voltage based on the voltage of the fifth node.

Abstract: A semiconductor device includes: a voltage clamping circuit including a plurality of first elements operating upon receiving a voltage having a first level and configured to output a clamp signal swinging in the first level by adjusting a voltage of an external input signal swinging in a second level more than twice the first level; a first buffer circuit configured to buffer the clamp signal; a level down shifter circuit configured to reduce the voltage of the clamp signal and output an internal input signal swinging in the first level between a predetermined reference voltage and a first power supply voltage higher than the reference voltage; and a second buffer circuit configured to buffer the internal input signal and transmits the internal input signal to a core circuit.

Abstract: A level shifter includes: an input circuit receiving an input signal swinging between a reference voltage and a first power supply voltage having a level higher than a level of the reference voltage; an output circuit outputting an output signal swinging between a second power supply voltage having a level higher than the level of the first power supply voltage and a third power supply voltage having a level higher than the level of the second power supply voltage; and a tolerant circuit connected between the input circuit and the output circuit, and configured to limit an output voltage of the input circuit to a range between the reference voltage and the second power supply voltage.

Abstract: An electro-static discharge protection device includes a substrate that includes a first well that has a first conductive type and a second well that has a second conductive type, and first to eighth diffusion regions formed on the first well and the second well. At least a portion of the diffusion regions formed in the first well are connected to a first electrode, and at least a portion of diffusion regions formed in a second well are connected to a second electrode. The contact between one of diffusion regions formed in the first well and an N well forms a trigger diode. A junction between one of diffusion regions formed in a second well and a P well forms a trigger diode. The trigger diodes are electrically connected to each other.

Abstract: An electrostatic discharge protection device includes: an emitter region disposed on a semiconductor substrate; a base region surrounding the emitter region; a first collector region surrounding the base region; a second collector region surrounding the first collector region; a second conductivity-type drift region below the emitter region, and being deeper than the base region; a second conductivity-type well region disposed below the base region, and having a junction interface with the second conductivity-type drift region; and a plurality of isolation portions disposed between the emitter region, the base region, and the first collector region and the second collector region.

Abstract: A semiconductor device includes a substrate including a P-well region, a gate electrode on the substrate, and a first region and a second region formed in the substrate on opposite sides adjacent to the gate electrode, the first region includes a first N-well region in the substrate and a second N-well region, a first impurity region, a second impurity region in the first N-well region, the second region includes a third impurity region in the substrate and a fourth impurity region in the third impurity region, a doping concentration of the second N-well region is greater than a doping concentration of the first N-well region, and a doping concentration of the second impurity region is greater than a doping concentration of the second N-well region.

Abstract: An electrostatic discharge (ESD) device having a small size, a low turn-on voltage, and a low on resistance and an ESD protection circuit including the ESD device are provided. The ESD device includes a well formed in a substrate to have a first conductive type, an active region being defined at an upper portion of the substrate, a plurality of fins extending in a first direction to have a structure protruding from the substrate, a first conductive impurity region formed with first conductive impurities, a second conductive impurity region formed with second conductive impurities, and a fin-cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction to cut each fin, wherein a bottom surface of the fin-cut isolation region is higher than a bottom surface of the active region.

Abstract: A semiconductor device includes first well regions in a substrate and spaced apart from each other, a connection doped region between the first well regions, and a first interconnection line electrically connected to the connection doped region through a first contact. The first well regions and the connection doped region include impurities of a first conductivity type, and a concentration of the impurities in the connection doped region is higher than that in the first well regions. The first well regions extend into the substrate to a depth larger than that of the connection doped region. A first portion of the connection doped region is disposed in the first well regions and a second portion of the connection doped region contacts the substrate.

Abstract: An electrostatic discharge protection device includes: an emitter region disposed on a semiconductor substrate; a base region surrounding the emitter region; a first collector region surrounding the base region; a second collector region surrounding the first collector region; a second conductivity-type drift region below the emitter region, and being deeper than the base region; a second conductivity-type well region disposed below the base region, and having a junction interface with the second conductivity-type drift region; and a plurality of isolation portions disposed between the emitter region, the base region, and the first collector region and the second collector region.

Abstract: An electrostatic discharge (ESD) device having a small size, a low turn-on voltage, and a low on resistance and an ESD protection circuit including the ESD device are provided. The ESD device includes a well formed in a substrate to have a first conductive type, an active region being defined at an upper portion of the substrate, a plurality of fins extending in a first direction to have a structure protruding from the substrate, a first conductive impurity region formed with first conductive impurities, a second conductive impurity region formed with second conductive impurities, and a fin-cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction to cut each fin, wherein a bottom surface of the fin-cut isolation region is higher than a bottom surface of the active region.

Abstract: A semiconductor device includes a substrate including a P-well region, a gate electrode on the substrate, and a first region and a second region formed in the substrate on opposite sides adjacent to the gate electrode, the first region includes a first N-well region in the substrate and a second N-well region, a first impurity region, a second impurity region in the first N-well region, the second region includes a third impurity region in the substrate and a fourth impurity region in the third impurity region, a doping concentration of the second N-well region is greater than a doping concentration of the first N-well region, and a doping concentration of the second impurity region is greater than a doping concentration of the second N-well region.

Abstract: A semiconductor device includes first well regions in a substrate and spaced apart from each other, a connection doped region between the first well regions, and a first interconnection line electrically connected to the connection doped region through a first contact. The first well regions and the connection doped region include impurities of a first conductivity type, and a concentration of the impurities in the connection doped region is higher than that in the first well regions. The first well regions extend into the substrate to a depth larger than that of the connection doped region. A first portion of the connection doped region is disposed in the first well regions and a second portion of the connection doped region contacts the substrate.

Abstract: A buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an input/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the pull down circuit through the pull up circuit does not exist when electrostatic discharge is received at the input/output pad.

Abstract: The buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an put/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the pull down circuit through the pull up circuit does not exist when electrostatic discharge is received at the input/output pad.

Abstract: The buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an put/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the pull down circuit through the pull up circuit does not exist when electrostatic discharge is received at the input/output pad.

Abstract: The buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an put/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the pull down circuit through the pull up circuit does not exist when electrostatic discharge is received at the input/output pad.