Abstract: A semiconductor device includes a first pad configured to receive and transmit a signal; a second pad to which a predetermined reference voltage is input; and an electrostatic protection circuit includes an emitter region electrically connected to the second pad and doped with a first conductivity-type impurity, a base region having a shape surrounding the emitter region in the first direction and the second direction and doped with a second conductivity-type impurity, different from the first conductivity-type impurity, a collector region connected to the first pad and having a shape surrounding the emitter region in the first direction and the second direction, and an impurity region disposed between the collector region and the base region and separated from the collector region and the base region by an element isolation film.

Abstract: A semiconductor device includes a substrate doped with first conductivity-type impurities, a first well doped with second conductivity-type impurities different from the first conductivity-type impurities, first active regions in the first well, the first active regions being doped with the first conductivity-type impurities and connected to a first pad through a first interconnection, second active regions outside the first well, the second active regions being doped with the second conductivity-type impurities and connected to a second pad through a second interconnection, third active regions around the first active regions in the first well and doped with the second conductivity-type impurities, and fourth active regions around the second active regions outside the first well and doped with the first conductivity-type impurities, wherein at least one of the third active regions and at least one of the fourth active regions are electrically connected to each other through a third interconnection.

Abstract: A device includes: a first silicon-controlled rectifier comprising a first PNP bipolar junction transistor (BJT) and a first NPN BJT in which bases and collectors are cross-coupled; and a field effect transistor (FET) configured to, based on an electrostatic discharge occurring between an anode of the first silicon-controlled rectifier and a cathode of the first silicon-controlled rectifier, trigger the first silicon-controlled rectifier. An emitter of the first PNP BJT corresponds to a plurality of first p+ regions being spaced apart from each other in a first direction. The FET is connected to the first silicon-controlled rectifier through at least one first n+ region disposed between the plurality of first p+ regions.

Abstract: The present disclosure relates to semiconductor devices. An example semiconductor device includes a first well region and a second well region isolated from each other by a first device isolation film; an NPN transistor provided by a first collector region formed in the first well region and including first conductivity-type impurities, and a first emitter region formed in the second well region and including the first conductivity-type impurities; a PNP transistor provided by a second emitter region formed in the first well region and including second conductivity-type impurities different from the first conductivity-type, and a second collector region formed in the second well region and including the second conductivity-type impurities; and an NMOS transistor including a source region and a drain region formed in the second well region and including the first conductivity-type impurities, and a gate structure disposed between the source region and the drain region.

Abstract: Provided is a device including a first well having a first conductivity type, a first gate electrode on the first well, a first region and a second region each having a second conductivity type on the first well with the first gate electrode disposed therebetween, a third region having the second conductivity type on the first well, and a fourth region having the first conductivity type on the first well. The first gate electrode and the first region are electrically connected to a first node, and the third region is electrically connected to a second node.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first power pad; a second power pad; a signal pad; a clamping circuit connected between the first power pad and the second power pad; a driving circuit connected to the signal pad and including a pull-up circuit and a pull-down circuit; and a first gate-off circuit connected to the pull-down circuit. The first gate-off circuit is configured to connect a gate of the pull-down circuit and a source of the pull-down circuit to each other during an electrostatic discharge (ESD) event in which a high voltage is applied to the signal pad, and control a current generated by the high voltage to flow to the clamping circuit.

Abstract: A semiconductor device includes: a voltage clamping circuit including a plurality of first elements operating upon receiving a voltage having a first level and configured to output a clamp signal swinging in the first level by adjusting a voltage of an external input signal swinging in a second level more than twice the first level; a first buffer circuit configured to buffer the clamp signal; a level down shifter circuit configured to reduce the voltage of the clamp signal and output an internal input signal swinging in the first level between a predetermined reference voltage and a first power supply voltage higher than the reference voltage; and a second buffer circuit configured to buffer the internal input signal and transmits the internal input signal to a core circuit.

Abstract: A level shifter includes: an input circuit receiving an input signal swinging between a reference voltage and a first power supply voltage having a level higher than a level of the reference voltage; an output circuit outputting an output signal swinging between a second power supply voltage having a level higher than the level of the first power supply voltage and a third power supply voltage having a level higher than the level of the second power supply voltage; and a tolerant circuit connected between the input circuit and the output circuit, and configured to limit an output voltage of the input circuit to a range between the reference voltage and the second power supply voltage.

Abstract: An electrostatic discharge clamp circuit includes a resistor connected between a first node and a second node, a first capacitor connected between the second node and a third node, a second capacitor connected between a fourth node and the third node, a third capacitor connected between a fifth node and the third node, a first inverter providing a power supply voltage or a voltage of the fourth node based on a voltage of the second node, a second inverter providing an output voltage of the first inverter or a voltage of the fifth node based on the voltage of the fourth node, a third inverter configured to provide an output voltage of the second inverter or the ground voltage based on the voltage of the fifth node.

Abstract: A device, including a first silicon controlled rectifier comprising a first anode connected to a first node, a first cathode connected to a pad, and a first gate; a second silicon controlled rectifier comprising a second anode connected to the pad, a second cathode connected to a second node, and a second gate; and a back diode forwardly connected from the second node to the first gate.

Abstract: Provided is a device including a first clamp circuit electrically connected between a first node and a second node, and a second clamp circuit electrically connected between the second node and a third node, wherein the first clamp circuit includes a first silicon controlled rectifier (SCR) including a first region of a first conductivity type electrically connected to the first node, a second region of a second conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type electrically connected to the second node, and a first gate electrode disposed over a channel region including a junction of the second region and the third region between the first region and the fourth region.

Abstract: A device including a first clamp circuit connected between a first node and a second node, wherein the first clamp circuit includes: a symmetric bipolar transistor comprising a control terminal, a first current terminal and a second current terminal, wherein the first current terminal and the second current terminal are symmetrical to each other with respect to the control terminal; a first bipolar transistor electrically connected to the symmetric bipolar transistor and to the first node; and a second bipolar transistor electrically connected to the symmetric bipolar transistor and to the second node.

Abstract: In an example method of analyzing an electrostatic discharge (ESD) network, input data characterizing a semiconductor device is received. The semiconductor device includes an input/output (I/O) pad, an ESD protection circuit, and at least one functional circuit. A common resistance of the ESD protection circuit is calculated based on the input data and using a plurality of resistances and at least one predetermined equation. The plurality of resistances are associated with the I/O pad, the ESD protection circuit, and the at least one functional circuit. A network analysis is performed on the semiconductor device by excluding the common resistance.

Abstract: A device including a silicon controlled rectifier including an anode and a cathode; at least one first transistor connected between the anode and a gate of the silicon controlled rectifier; and a second transistor including a source connected to one from among the cathode or the anode, and a drain connected to a body of the at least one first transistor.

Abstract: An electrostatic discharge clamp circuit includes a resistor connected between a first node and a second node, a first capacitor connected between the second node and a third node, a second capacitor connected between a fourth node and the third node, a third capacitor connected between a fifth node and the third node, a first inverter providing a power supply voltage or a voltage of the fourth node based on a voltage of the second node, a second inverter providing an output voltage of the first inverter or a voltage of the fifth node based on the voltage of the fourth node, a third inverter configured to provide an output voltage of the second inverter or the ground voltage based on the voltage of the fifth node.

Abstract: A level shifter includes: an input circuit receiving an input signal swinging between a reference voltage and a first power supply voltage having a level higher than a level of the reference voltage; an output circuit outputting an output signal swinging between a second power supply voltage having a level higher than the level of the first power supply voltage and a third power supply voltage having a level higher than the level of the second power supply voltage; and a tolerant circuit connected between the input circuit and the output circuit, and configured to limit an output voltage of the input circuit to a range between the reference voltage and the second power supply voltage.

Abstract: A semiconductor device includes: a voltage clamping circuit including a plurality of first elements operating upon receiving a voltage having a first level and configured to output a clamp signal swinging in the first level by adjusting a voltage of an external input signal swinging in a second level more than twice the first level; a first buffer circuit configured to buffer the clamp signal; a level down shifter circuit configured to reduce the voltage of the clamp signal and output an internal input signal swinging in the first level between a predetermined reference voltage and a first power supply voltage higher than the reference voltage; and a second buffer circuit configured to buffer the internal input signal and transmits the internal input signal to a core circuit.

Abstract: An electrostatic discharge protection device includes: an emitter region disposed on a semiconductor substrate; a base region surrounding the emitter region; a first collector region surrounding the base region; a second collector region surrounding the first collector region; a second conductivity-type drift region below the emitter region, and being deeper than the base region; a second conductivity-type well region disposed below the base region, and having a junction interface with the second conductivity-type drift region; and a plurality of isolation portions disposed between the emitter region, the base region, and the first collector region and the second collector region.

Abstract: A semiconductor device includes a substrate including a P-well region, a gate electrode on the substrate, and a first region and a second region formed in the substrate on opposite sides adjacent to the gate electrode, the first region includes a first N-well region in the substrate and a second N-well region, a first impurity region, a second impurity region in the first N-well region, the second region includes a third impurity region in the substrate and a fourth impurity region in the third impurity region, a doping concentration of the second N-well region is greater than a doping concentration of the first N-well region, and a doping concentration of the second impurity region is greater than a doping concentration of the second N-well region.

Abstract: An electrostatic discharge (ESD) device having a small size, a low turn-on voltage, and a low on resistance and an ESD protection circuit including the ESD device are provided. The ESD device includes a well formed in a substrate to have a first conductive type, an active region being defined at an upper portion of the substrate, a plurality of fins extending in a first direction to have a structure protruding from the substrate, a first conductive impurity region formed with first conductive impurities, a second conductive impurity region formed with second conductive impurities, and a fin-cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction to cut each fin, wherein a bottom surface of the fin-cut isolation region is higher than a bottom surface of the active region.