Patents by Inventor Chan-hee JEONG

Chan-hee JEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146103
    Abstract: Embodiments of the inventive concept provide a wireless power apparatus for a substrate treating apparatus and a manufacturing method for the wireless power apparatus for the substrate treating apparatus for preventing a heat generation by preventing a generation of an eddy current in a coupling element, if the coupling element is used around an outer housing at which an induced magnetic field is formed. The inventive concept provides a wireless power apparatus for a substrate treating apparatus.
    Type: Application
    Filed: April 26, 2023
    Publication date: May 2, 2024
    Applicant: SEMES CO., LTD.
    Inventors: Chan Young Choi, Ki Won Han, Wan Hee Jeong, Kyo Bong Kim, Hee Chan Kim, Doo Hyun Baek, Sang-Oh Kim, Hee Jae Byun
  • Publication number: 20240073416
    Abstract: The present invention relates to an apparatus and method for encoding and decoding an image by skip encoding. The image-encoding method by skip encoding, which performs intra-prediction, comprises: performing a filtering operation on the signal which is reconstructed prior to an encoding object signal in an encoding object image; using the filtered reconstructed signal to generate a prediction signal for the encoding object signal; setting the generated prediction signal as a reconstruction signal for the encoding object signal; and not encoding the residual signal which can be generated on the basis of the difference between the encoding object signal and the prediction signal, thereby performing skip encoding on the encoding object signal.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicants: Electronics and Telecommunications Research Institute, Kwangwoon University Industry-Academic Collaboration Foundation, Universily-lndustry Cooperation Group of Kyung Hee University
    Inventors: Sung Chang LIM, Ha Hyun LEE, Se Yoon JEONG, Hui Yong KIM, Suk Hee CHO, Jong Ho KIM, Jin Ho LEE, Jin Soo CHOI, Jin Woong KIM, Chie Teuk AHN, Dong Gyu SIM, Seoung Jun OH, Gwang Hoon PARK, Sea Nae PARK, Chan Woong JEON
  • Patent number: 11031307
    Abstract: A semiconductor package includes a buffer wafer including: a first surface; and a second surface opposite to the first surface, a stacked structure including a plurality of chips being stacked on the first surface of the buffer wafer; a first detection line formed around a periphery of the stacked structure on the first surface of the buffer wafer; and a mold layer covering the stacked structure, the first detection line and the first surface of the buffer wafer.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan Hee Jeong, Hyun Ki Seo, Joo Hyung Lee, Jae Gil Lim
  • Publication number: 20200294869
    Abstract: A semiconductor package includes a buffer wafer including: a first surface; and a second surface opposite to the first surface, a stacked structure including a plurality of chips being stacked on the first surface of the buffer wafer; a first detection line formed around a periphery of the stacked structure on the first surface of the buffer wafer; and a mold layer covering the stacked structure, the first detection line and the first surface of the buffer wafer.
    Type: Application
    Filed: November 15, 2019
    Publication date: September 17, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan Hee JEONG, Hyun Ki Seo, Joo Hyung Lee, Jae Gil Lim
  • Patent number: 10204869
    Abstract: An integrated circuit package includes at least one first chip mounted in a first region of a mounting surface of a printed circuit board, a molding unit covering the mounting surface and surrounding the at least one first chip, an electromagnetic shielding film covering a surface of the molding unit and surrounding the at least one first chip, and a second chip mounted in a second region of the mounting surface. The second chip is exposed outside the electromagnetic shielding film and is spaced apart from the printed circuit board, with the molding unit being between the second chip and the printed circuit board.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-hee Jeong, Soo-jae Park, Young-hoon Kim, In-ku Kang, Hee-yeol Kim
  • Publication number: 20180233458
    Abstract: An integrated circuit package includes at least one first chip mounted in a first region of a mounting surface of a printed circuit board, a molding unit covering the mounting surface and surrounding the at least one first chip, an electromagnetic shielding film covering a surface of the molding unit and surrounding the at least one first chip, and a second chip mounted in a second region of the mounting surface. The second chip is exposed outside the electromagnetic shielding film and is spaced apart from the printed circuit board, with the molding unit being between the second chip and the printed circuit board.
    Type: Application
    Filed: April 10, 2018
    Publication date: August 16, 2018
    Inventors: Chan-hee JEONG, Soo-jae PARK, Young-hoon KIM, In-ku KANG, Hee-yeol KIM
  • Patent number: 9978693
    Abstract: An integrated circuit package includes at least one first chip mounted in a first region of a mounting surface of a printed circuit board, a molding unit covering the mounting surface and surrounding the at least one first chip, an electromagnetic shielding film covering a surface of the molding unit and surrounding the at least one first chip, and a second chip mounted in a second region of the mounting surface. The second chip is exposed outside the electromagnetic shielding film and is spaced apart from the printed circuit board, with the molding unit being between the second chip and the printed circuit board.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-hee Jeong, Soo-jae Park, Young-hoon Kim, In-ku Kang, Hee-yeol Kim
  • Publication number: 20180090449
    Abstract: An integrated circuit package includes at least one first chip mounted in a first region of a mounting surface of a printed circuit board, a molding unit covering the mounting surface and surrounding the at least one first chip, an electromagnetic shielding film covering a surface of the molding unit and surrounding the at least one first chip, and a second chip mounted in a second region of the mounting surface. The second chip is exposed outside the electromagnetic shielding film and is spaced apart from the printed circuit board, with the molding unit being between the second chip and the printed circuit board.
    Type: Application
    Filed: May 25, 2017
    Publication date: March 29, 2018
    Inventors: Chan-hee JEONG, Soo-jae PARK, Young-hoon KIM, In-ku KANG, Hee-yeol KIM