Patents by Inventor Chan-hee JEONG

Chan-hee JEONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor package, buffer wafer for semiconductor package, and method of manufacturing semiconductor package
    Patent number: 11031307
    Abstract: A semiconductor package includes a buffer wafer including: a first surface; and a second surface opposite to the first surface, a stacked structure including a plurality of chips being stacked on the first surface of the buffer wafer; a first detection line formed around a periphery of the stacked structure on the first surface of the buffer wafer; and a mold layer covering the stacked structure, the first detection line and the first surface of the buffer wafer.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan Hee Jeong, Hyun Ki Seo, Joo Hyung Lee, Jae Gil Lim
  • SEMICONDUCTOR PACKAGE, BUFFER WAFER FOR SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
    Publication number: 20200294869
    Abstract: A semiconductor package includes a buffer wafer including: a first surface; and a second surface opposite to the first surface, a stacked structure including a plurality of chips being stacked on the first surface of the buffer wafer; a first detection line formed around a periphery of the stacked structure on the first surface of the buffer wafer; and a mold layer covering the stacked structure, the first detection line and the first surface of the buffer wafer.
    Type: Application
    Filed: November 15, 2019
    Publication date: September 17, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan Hee JEONG, Hyun Ki Seo, Joo Hyung Lee, Jae Gil Lim
  • Integrated circuit package including shielding between adjacent chips
    Patent number: 10204869
    Abstract: An integrated circuit package includes at least one first chip mounted in a first region of a mounting surface of a printed circuit board, a molding unit covering the mounting surface and surrounding the at least one first chip, an electromagnetic shielding film covering a surface of the molding unit and surrounding the at least one first chip, and a second chip mounted in a second region of the mounting surface. The second chip is exposed outside the electromagnetic shielding film and is spaced apart from the printed circuit board, with the molding unit being between the second chip and the printed circuit board.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-hee Jeong, Soo-jae Park, Young-hoon Kim, In-ku Kang, Hee-yeol Kim
  • INTEGRATED CIRCUIT PACKAGE
    Publication number: 20180233458
    Abstract: An integrated circuit package includes at least one first chip mounted in a first region of a mounting surface of a printed circuit board, a molding unit covering the mounting surface and surrounding the at least one first chip, an electromagnetic shielding film covering a surface of the molding unit and surrounding the at least one first chip, and a second chip mounted in a second region of the mounting surface. The second chip is exposed outside the electromagnetic shielding film and is spaced apart from the printed circuit board, with the molding unit being between the second chip and the printed circuit board.
    Type: Application
    Filed: April 10, 2018
    Publication date: August 16, 2018
    Inventors: Chan-hee JEONG, Soo-jae PARK, Young-hoon KIM, In-ku KANG, Hee-yeol KIM
  • Integrated circuit package, method of fabricating the same, and wearable device including integrated circuit package
    Patent number: 9978693
    Abstract: An integrated circuit package includes at least one first chip mounted in a first region of a mounting surface of a printed circuit board, a molding unit covering the mounting surface and surrounding the at least one first chip, an electromagnetic shielding film covering a surface of the molding unit and surrounding the at least one first chip, and a second chip mounted in a second region of the mounting surface. The second chip is exposed outside the electromagnetic shielding film and is spaced apart from the printed circuit board, with the molding unit being between the second chip and the printed circuit board.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-hee Jeong, Soo-jae Park, Young-hoon Kim, In-ku Kang, Hee-yeol Kim
  • INTEGRATED CIRCUIT PACKAGE, METHOD OF FABRICATING THE SAME, AND WEARABLE DEVICE INCLUDING INTEGRATED CIRCUIT PACKAGE
    Publication number: 20180090449
    Abstract: An integrated circuit package includes at least one first chip mounted in a first region of a mounting surface of a printed circuit board, a molding unit covering the mounting surface and surrounding the at least one first chip, an electromagnetic shielding film covering a surface of the molding unit and surrounding the at least one first chip, and a second chip mounted in a second region of the mounting surface. The second chip is exposed outside the electromagnetic shielding film and is spaced apart from the printed circuit board, with the molding unit being between the second chip and the printed circuit board.
    Type: Application
    Filed: May 25, 2017
    Publication date: March 29, 2018
    Inventors: Chan-hee JEONG, Soo-jae PARK, Young-hoon KIM, In-ku KANG, Hee-yeol KIM