Abstract: An integrated circuit includes a first circuit, formed based on one or more Group III-V compound materials, that is configured to operate with a first voltage range. The integrated circuit includes a second circuit, also formed based on the one or more Group III-V compound materials, that is operatively coupled to the first circuit and configured to operate with a second voltage range, wherein the second voltage range is substantially higher than the first voltage range. The integrated circuit includes a set of first test terminals connected to the first circuit. The integrated circuit includes a set of second test terminals connected to the second circuit. Test signals applied to the set of first test terminals and to the set of second test terminals, respectively, are independent from each other.

Abstract: Provided herein is a contrast agent composition comprising a contrast agent, such as a gadolinium chelate contrast agent, and a perfluorocarbon. Provided herein also is a method of imaging a patient's bladder or other organs containing a cavity, using MRI using a contrast agent composition comprising a contrast agent, such as a gadolinium chelate contrast agent, and a perfluorocarbon.

Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

Abstract: Apparatus and circuits including transistors with different polarizations and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion and a second active portion; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first active portion has a material composition different from that of the second active portion.

Abstract: A system for radio frequency (RF) residual sideband (RSB) calibration includes a complex (in phase/quadrature (I/Q)) signal receiver, a signal generator configured to generate a transmit (Tx) signal, a first phase shifter operably coupled to the real signal transmitter, a first signal combiner configured to combine a receive (Rx) signal with the transmit (Tx) signal to generate a first combined signal, a second phase shifter configured to provide a selected phase shift to the first combined signal, and a complex downconverter configured to generate an in phase Rx signal and a quadrature Rx signal alternatively using an in phase LO signal and a quadrature LO signal to generate one or more signals indicative of relative Tx-Rx LO phase (?), amplitude (A), Tx LO I/Q phase mismatch (?), Rx I/Q amplitude mismatch (?), and Rx I/Q phase mismatch (?) at the output of the complex receiver.

Abstract: An apparatus, including: a clock source configured to generate a local oscillator (LO) clock signal; a radio frequency digital-to-analog converter (RF DAC) configured to generate a radio frequency (RF) signal based on a data signal and the LO clock signal; and an idle data detector configured to: detect a stream of idle data in the data signal; and disable providing the LO clock signal to at least a portion of the RF DAC in response to detecting the stream of idle data.

Abstract: A semiconductor device include: a first bus waveguide; a first silicon ring optically coupled to the first bus waveguide; a backup silicon ring optically coupled to the first bus waveguide; a first heater and a second heater configured to heat the first silicon ring and the backup silicon ring, respectively; and a first switch, where the first switch is configured to electrically couple the first silicon ring to a first radio frequency (RF) circuit when the first switch is at a first switching position, and is configured to electrically couple the backup silicon ring to the first RF circuit when the first switch is at a second switching position.

Abstract: An apparatus including: a transmitter output impedance matching circuit including an inductive element; a low noise amplifier (LNA) including a first field effect transistor (PET); a receiver input impedance matching circuit, including: a transformer including a first winding and a second winding; and a capacitor coupled in series with the first winding between a first end of the inductive element and a gate of the first FET, wherein the second winding is coupled to a second end of the inductive element; and a radio frequency (RF) port coupled between the first end of the inductive element and the capacitor.

Abstract: This disclosure is directed to a circuit that includes a substrate, a target device on the substrate, and an electrostatic discharge (ESD) device electrically coupled to the target device. The ESD device includes an ESD detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the ESD detection circuit and configured to trigger in response to an ESD event on the first or second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and configured to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and configured to discharge a remaining current passing through the rectifier circuit.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor package structure including a first integrated circuit (IC) chip overlying a base structure. An electrical IC chip overlies the base structure and is disposed around the first IC chip. The electrical IC chip is electrically coupled to the first IC chip. A photonic IC chip overlies the base structure and is electrically coupled to the electrical IC chip. The photonic IC chip is configured to receive an input optical signal. The photonic IC chip is adjacent to the electrical IC chip.

Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

Abstract: Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.

Abstract: Methods of fabricating optical devices with high refractive index materials are disclosed. The method includes forming a first oxide layer on a substrate and forming a patterned template layer with first and second trenches on the first oxide layer. A material of the patterned template layer has a first refractive index. The method further includes forming a first portion of a waveguide and a first portion of an optical coupler within the first and second trenches, respectively, forming a second portion of the waveguide and a second portion of the optical coupler on a top surface of the patterned template layer, and depositing a cladding layer on the second portions of the waveguide and optical coupler. The waveguide and the optical coupler include materials with a second refractive index that is greater than the first refractive index.

Abstract: The present disclosure provides a photo sensing device and a method for forming a photo sensing device. The photo sensing device includes a substrate, a photosensitive member, a superlattice layer and a diffusion barrier structure. The substrate includes a silicon layer at a front surface. The photosensitive member extends into and at least partially surrounded by the silicon layer, wherein an upper portion of the photosensitive member protruding from the silicon layer has a top surface and a facet tapering toward the top surface. The superlattice layer is disposed between the photosensitive member and the silicon layer. The diffusion barrier structure is disposed at a first side of the photosensitive member and a bottom of the diffusion barrier structure is at a level below a top surface of the silicon layer, wherein at least a portion of the diffusion barrier structure is laterally surrounded by the silicon layer.

Abstract: An integrated circuit includes a first circuit, formed based on one or more Group III-V compound materials, that is configured to operate with a first voltage range. The integrated circuit includes a second circuit, also formed based on the one or more Group III-V compound materials, that is operatively coupled to the first circuit and configured to operate with a second voltage range, wherein the second voltage range is substantially higher than the first voltage range. The integrated circuit includes a set of first test terminals connected to the first circuit. The integrated circuit includes a set of second test terminals connected to the second circuit. Test signals applied to the set of first test terminals and to the set of second test terminals, respectively, are independent from each other.

Abstract: According to the present invention, there are provided a preparation method of a water-soluble acryl-modified phenolic-modified epoxy resin including preparing an acrylic copolymer resin containing a carboxylic acid group; preparing a phenolic-modified epoxy resin by reacting an epoxy resin with a phenolic compound; preparing an acryl-modified phenolic-modified epoxy resin by ester-reacting the acrylic copolymer resin with the phenolic-modified epoxy resin; and preparing a water-soluble acryl-modified phenolic-modified epoxy resin by neutralizing the acryl-modified phenolic-modified epoxy resin, a water-soluble acryl-modified phenolic-modified epoxy resin prepared thereby, and an aqueous paint composition including the same. According to the present invention, the water-soluble acryl-modified phenolic-modified epoxy resin and the aqueous coating composition including the same may be applied to most of conventional uses in which the epoxy resin is used due to excellent various physical properties.

Abstract: The present disclosure relates to transmitting and receiving beam information in a wireless communication system. An operation of a receiving end includes: generating a signal indicating two or more analogue transmission beams which are allocable to the receiving end; and transmitting the signal. In addition, the present disclosure includes other embodiments different from the embodiment described above.

Abstract: The present disclosure describes a semiconductor device having artificial field plates. The semiconductor device includes a first gallium nitride (GaN) layer on a substrate, an aluminum gallium nitride (AlGaN) layer on the first GaN layer, and a second GaN layer on the AlGaN layer. The first and second GaN layers includes different types of dopants. The semiconductor device further includes a gate contact structure in contact with the second GaN layer, first and second source/drain (S/D) contact structures in contact with the AlGaN layer, one or more artificial field plates between the gate contact structure and the first S/D contact structure. The first and second S/D contact structures are disposed at opposite sides of the gate contact structure. The one or more artificial field plates are separated from the first and second S/D contact structures and above the AlGaN layer.

Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

Abstract: Integrated optical devices and methods of forming the same are disclosed. A method of forming an integrated optical device includes the following steps. A substrate is provided. The substrate includes, from bottom to top, a first semiconductor layer, an insulating layer and a second semiconductor layer. The second semiconductor layer is patterned to form a waveguide pattern. A surface smoothing treatment is performed to the waveguide pattern until a surface roughness Rz of the waveguide pattern is equal to or less than a desired value. A cladding layer is formed over the waveguide pattern.