Patents by Inventor Chan-Hong Park

Chan-Hong Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6844761
    Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: January 18, 2005
    Assignee: Berkana Wireless, Inc.
    Inventors: Sang Jin Byun, Beomsup Kim, Chan-Hong Park
  • Publication number: 20040004500
    Abstract: A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.
    Type: Application
    Filed: May 13, 2003
    Publication date: January 8, 2004
    Applicant: Berkana Wireless, Inc.
    Inventors: Sang Jin Byun, Beomsup Kim, Chan-Hong Park
  • Publication number: 20040000937
    Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.
    Type: Application
    Filed: May 12, 2003
    Publication date: January 1, 2004
    Applicant: Berkana Wireless, Inc.
    Inventors: Sang Jin Byun, Beomsup Kim, Chan-Hong Park
  • Patent number: 6501336
    Abstract: Disclosed is a self-calibration device for calibrating a phase difference between output waveforms of a ring oscillator, comprising: a voltage-controlled oscillator adapted to adjust the transition time of an output signal according to an inputting of a control voltage for controlling the phase offset and generate the adjusted output signal; a divider adapted to divide a frequency of the output signal generated from the voltage-controlled oscillator by a fractional number to generate a plurality of output waveforms having different phases with them having an identical phase difference each other; a phase-locked loop (PLL) circuit adapted to correctly make a frequency and phase of the output signal of the divider coincident with those of a system clock, the phase-locked loop (PLL) circuit including at least a phase-frequency detecting means adapted to compare the frequency and phase of the output signal with those of the system clock and to output a result of the comparison; and a phase offset calibrating loop
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: December 31, 2002
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Beomsup Kim, Chan-Hong Park
  • Publication number: 20010028276
    Abstract: Disclosed is a self-calibration device for calibrating a phase difference between output waveforms of a ring oscillator, comprising: a voltage-controlled oscillator adapted to adjust the transition time of an output signal according to an inputting of a control voltage for controlling the phase offset and generate the adjusted output signal; a divider adapted to divide a frequency of the output signal generated from the voltage-controlled oscillator by a fractional number to generate a plurality of output waveforms having different phases with them having an identical phase difference each other; a phase-locked loop (PLL) circuit adapted to correctly make a frequency and phase of the output signal of the divider coincident with those of a system clock, the phase-locked loop (PLL) circuit including at least a phase-frequency detecting means adapted to compare the frequency and phase of the output signal with those of the system clock and to output a result of the comparison; and a phase offset calibrating loop
    Type: Application
    Filed: January 18, 2001
    Publication date: October 11, 2001
    Inventors: Beomsup Kim, Chan-Hong Park