Abstract: A mobile communication device comprises a plurality of receivers, a phase detection circuit, and a DC offset calibration circuit. Each receiver comprises a receiver chain and a divide-by-2 circuit that supplies Local Oscillating (LO) signal for the receiver chain. The LO signals leak to each receiver chain and create an undesirable DC offset voltage. The DC offset depends on an LNA gain and a phase relation among the LO leakages. In a first novel aspect, a two-dimensional DC offset calibration (DCOC) table is prepared for each receiver chain. In a second novel aspect, the phase detection circuit detects the phase relation among the LO leakages for each receiver chain. Based on the LNA gain and the detected phase relation of each receiver chain, a DCOC code is selected from a corresponding DCOC table such that the calibration circuit calibrates the DC offset for each receiver effectively and efficiently.

Abstract: A method for calibrating the loop bandwidth of a phase-locked loop (PLL) is described. At least one resistor in the PLL filter is tuned in accordance with the frequency of an input reference signal. One or more capacitors in the PLL filter are tuned in accordance with the frequency of the input reference signal. Output pulses of one or more voltage controlled oscillators (VCO) are counted. A first charge pump current associated with a target loop bandwidth is counted in accordance with the counted output pulses. A programmable charge pump current is tuned to the calculated first charge pump current.

Abstract: A method for calibrating the loop bandwidth of a phase-locked loop (PLL) is described. At least one resistor in the PLL filter is tuned in accordance with the frequency of an input reference signal. One or more capacitors in the PLL filter are tuned in accordance with the frequency of the input reference signal. Output pulses of one or more voltage controlled oscillators (VCO) are counted. A first charge pump current associated with a target loop bandwidth is counted in accordance with the counted output pulses. A Programmable charge pump current is tuned to the calculated first charge pump current.

Abstract: Techniques for writing to registers associated with MIMO signal paths are disclosed. In are embodiment, a controller writes a common value to all registers corresponding to the same operational parameter or parameters, for all signal paths in the MIMO transmitter or receiver. The controller then updates the register in any signal path whose operational paramater differs from the common value, by accumulating a value to the value already in the register, or by replacing the value already in the register with a different value.

Abstract: A plasma display panel (PDP) filter having a high transparency and no exterior defect can be simply prepared by a method comprising the steps of a) laminating a conductive mesh film having a metallic mesh layer formed on a base film, on a transparent glass substrate such that the base film of the conductive mesh film comes in contact with the transparent glass substrate, to obtain laminate A; b) forming a transparent adhesive layer on one surface of an optic film, to obtain laminate B; c) laminating laminate A and laminate B such that the adhesive layer of laminate B comes in contact with the metallic mesh layer of laminate A, to obtain laminate C; and d) heating and pressing laminate C in an autoclave to allow the adhesive layer of laminate B attach to the metallic mesh layer of laminate A.

Abstract: The present invention relates to a method for fabricating a front filter for a plasma display panel (PDP). In particular, the present invention relates to a front filter for a PDP comprising functional films including a conductive mesh film (2) having a black treated layer (2a), an optical film (1c) and an antireflection film (4) laminated on a glass substrate (3), wherein a transparent glass substrate (3) is used without a black ceramic stripe, which is formed at the rear side of the glass substrate (3) to improve visibility. Instead, composition and thickness of the oxide film forming the black treated layer (2a) of the conductive mesh film (2) are adjusted to attain comparable or better visibility, as compared with conventional filters. The minimized one-step fabricating process of the present invention provides advantages in terms of cost effectiveness and environment friendliness.

Abstract: A system and method are disclosed for providing a FSK demodulator using DLL and a demodulating method which detects a time order of the rising edges of square waves that correspond to two modulation frequencies and an in-between frequency and demodulates the relevant frequencies into data. The FSK demodulator includes a band-pass filter, an amplitude limiter for converting a waveform of the frequency filtered into a square wave, a delay line for receiving the square wave from the amplitude limiter and delaying the square wave for a delay time, a delayed flip-flop (DFF) for receiving an output signal from the amplitude limiter and an output signal from the delay line, determining which rising edge of the two input signals is earlier at a given time, and outputting the result of the determination as data, and a DLL circuit that locks the delay time of the delay line.

Abstract: A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

Abstract: A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

Abstract: Disclosed is a self-calibration device for calibrating a phase difference between output waveforms of a ring oscillator, comprising: a voltage-controlled oscillator adapted to adjust the transition time of an output signal according to an inputting of a control voltage for controlling the phase offset and generate the adjusted output signal; a divider adapted to divide a frequency of the output signal generated from the voltage-controlled oscillator by a fractional number to generate a plurality of output waveforms having different phases with them having an identical phase difference each other; a phase-locked loop (PLL) circuit adapted to correctly make a frequency and phase of the output signal of the divider coincident with those of a system clock, the phase-locked loop (PLL) circuit including at least a phase-frequency detecting means adapted to compare the frequency and phase of the output signal with those of the system clock and to output a result of the comparison; and a phase offset calibrating loop

Abstract: Disclosed is a self-calibration device for calibrating a phase difference between output waveforms of a ring oscillator, comprising: a voltage-controlled oscillator adapted to adjust the transition time of an output signal according to an inputting of a control voltage for controlling the phase offset and generate the adjusted output signal; a divider adapted to divide a frequency of the output signal generated from the voltage-controlled oscillator by a fractional number to generate a plurality of output waveforms having different phases with them having an identical phase difference each other; a phase-locked loop (PLL) circuit adapted to correctly make a frequency and phase of the output signal of the divider coincident with those of a system clock, the phase-locked loop (PLL) circuit including at least a phase-frequency detecting means adapted to compare the frequency and phase of the output signal with those of the system clock and to output a result of the comparison; and a phase offset calibrating loop