Patents by Inventor Chan-Hsiang Weng
Chan-Hsiang Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11290094Abstract: An input buffer using a frequency dependent impedance circuit to compensate for nonlinearity in low frequency is shown. In a pseudo-differential architecture, a frequency-dependent impedance circuit is coupled between the drain of a positive input transistor of the flipped voltage follower and the drain of a negative input transistor of the flipped voltage follower. In a single-ended architecture, the frequency-dependent impedance circuit is coupled between the drain of an input transistor of the flipped voltage follower and an alternating current ground. The frequency-dependent impedance circuit includes a capacitor.Type: GrantFiled: October 22, 2020Date of Patent: March 29, 2022Assignee: MEDIATEK SINGAPORE PTE. LTD.Inventors: Tao He, Chan-Hsiang Weng, Su-Hao Wu
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Patent number: 11121720Abstract: The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.Type: GrantFiled: July 20, 2020Date of Patent: September 14, 2021Assignee: MEDIATEK INC.Inventors: Chan-Hsiang Weng, Hung-Yi Hsieh, Tzu-An Wei, Ting-Yang Wang
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Publication number: 20210152164Abstract: An input buffer using a frequency dependent impedance circuit to compensate for nonlinearity in low frequency is shown. In a pseudo-differential architecture, a frequency-dependent impedance circuit is coupled between the drain of a positive input transistor of the flipped voltage follower and the drain of a negative input transistor of the flipped voltage follower. In a single-ended architecture, the frequency-dependent impedance circuit is coupled between the drain of an input transistor of the flipped voltage follower and an alternating current ground. The frequency-dependent impedance circuit includes a capacitor.Type: ApplicationFiled: October 22, 2020Publication date: May 20, 2021Inventors: Tao HE, Chan-Hsiang WENG, Su-Hao WU
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Patent number: 10979069Abstract: A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal.Type: GrantFiled: March 4, 2020Date of Patent: April 13, 2021Assignee: MEDIATEK INC.Inventors: Tien-Yu Lo, Chan-Hsiang Weng, Su-Hao Wu
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Patent number: 10924129Abstract: The present invention provides a time-interleaved analog-to-digital converter device, wherein the time-interleaved analog-to-digital converter device includes a random number generator, a plurality of ADCs and an output circuit. The random number generator is configured to generate a random number sequence. The plurality of ADCs are configured to receive an analog input signal to generate a plurality of digital signals, respectively, and each ADC is further configured to generate a selection signal according to the random number sequence. The output circuit is configured to select one of the digital signals according to the selection signals generated by the ADCs, to generate a digital output signal.Type: GrantFiled: March 25, 2020Date of Patent: February 16, 2021Assignee: MEDIATEK INC.Inventors: Su-Hao Wu, Chan-Hsiang Weng
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Publication number: 20210044301Abstract: The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.Type: ApplicationFiled: July 20, 2020Publication date: February 11, 2021Inventors: Chan-Hsiang Weng, Hung-Yi Hsieh, Tzu-An Wei, Ting-Yang Wang
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Publication number: 20200343899Abstract: The present invention provides a time-interleaved analog-to-digital converter device, wherein the time-interleaved analog-to-digital converter device includes a random number generator, a plurality of ADCs and an output circuit. The random number generator is configured to generate a random number sequence. The plurality of ADCs are configured to receive an analog input signal to generate a plurality of digital signals, respectively, and each ADC is further configured to generate a selection signal according to the random number sequence. The output circuit is configured to select one of the digital signals according to the selection signals generated by the ADCs, to generate a digital output signal.Type: ApplicationFiled: March 25, 2020Publication date: October 29, 2020Inventors: Su-Hao Wu, Chan-Hsiang Weng
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Publication number: 20200295776Abstract: A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal.Type: ApplicationFiled: March 4, 2020Publication date: September 17, 2020Inventors: Tien-Yu Lo, Chan-Hsiang Weng, Su-Hao Wu
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Patent number: 10483947Abstract: The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.Type: GrantFiled: October 11, 2018Date of Patent: November 19, 2019Assignee: MEDIATEK INC.Inventors: Tien-Yu Lo, Chan-Hsiang Weng, Patrick Cooney, Tsung-Kai Kao, Stacy Ho
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Patent number: 10432214Abstract: A signal processing apparatus has a multi-bit quantizer and a processing circuit. The multi-bit quantizer determines and outputs code segments of a multi-bit output code sequentially. The code segments include a first code segment and a second code segment. The processing circuit generates digital outputs according to the code segments, respectively. The digital outputs include a first digital output derived from a first code segment and a second digital output derived from a second code segment. A first transfer function between the first digital output and the first code segment is different from a second transfer function between the second digital output and the second code segment.Type: GrantFiled: November 14, 2018Date of Patent: October 1, 2019Assignee: MEDIATEK INC.Inventors: Chan-Hsiang Weng, Tien-Yu Lo
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Publication number: 20190288672Abstract: The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.Type: ApplicationFiled: October 11, 2018Publication date: September 19, 2019Inventors: Tien-Yu LO, Chan-Hsiang WENG, Patrick Cooney, Tsung-Kai KAO, Stacy HO
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Publication number: 20190199368Abstract: A signal processing apparatus has a multi-bit quantizer and a processing circuit. The multi-bit quantizer determines and outputs code segments of a multi-bit output code sequentially. The code segments include a first code segment and a second code segment. The processing circuit generates digital outputs according to the code segments, respectively. The digital outputs include a first digital output derived from a first code segment and a second digital output derived from a second code segment. A first transfer function between the first digital output and the first code segment is different from a second transfer function between the second digital output and the second code segment.Type: ApplicationFiled: November 14, 2018Publication date: June 27, 2019Inventors: Chan-Hsiang Weng, Tien-Yu Lo
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Patent number: 10141948Abstract: To convert a first stage input to a digital output, a delta-sigma modulator, an analog-to-digital converter and an associated signal conversion method based on an MASH structure are provided. The analog-to-digital converter includes the delta-sigma modulator and a sample and hold circuit. The delta-sigma modulator includes a first signal converter, a second signal converter and a digital cancellation logic. The first signal converter converts the first stage input to a first converted output. The first signal converter shapes a first stage quantization error to generate a second stage input. The first stage input and the second stage input are analog signals. The second signal converter converts the second stage input to a second converted output. The digital cancellation logic generates a digital output according to the first converted output and the second converted output.Type: GrantFiled: May 4, 2017Date of Patent: November 27, 2018Assignee: MediaTek Inc.Inventors: Chan-Hsiang Weng, Tien-Yu Lo
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Patent number: 9859914Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter module, a quantizer, a delta-sigma truncator, a digital filter module, and an output circuit. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter module is arranged for filtering the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a first digital signal according to the filtered summation signal. The delta-sigma truncator is arranged for truncating the first digital signal to generate a second digital signal. The digital filter module is arranged for filtering the first digital signal and the second digital signal to generate a filtered first digital signal and a filtered second digital signal, respectively. The output circuit is arranged for generating an output signal according to the filtered first digital signal and the filtered second digital signal.Type: GrantFiled: July 11, 2017Date of Patent: January 2, 2018Assignee: MEDIATEK INC.Inventors: Chan-Hsiang Weng, Tien-Yu Lo
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Publication number: 20170353191Abstract: To convert a first stage input to a digital output, a delta-sigma modulator, an analog-to-digital converter and an associated signal conversion method based on an MASH structure are provided. The analog-to-digital converter includes the delta-sigma modulator and a sample and hold circuit. The delta-sigma modulator includes a first signal converter, a second signal converter and a digital cancellation logic. The first signal converter converts the first stage input to a first converted output. The first signal converter shapes a first stage quantization error to generate a second stage input. The first stage input and the second stage input are analog signals. The second signal converter converts the second stage input to a second converted output. The digital cancellation logic generates a digital output according to the first converted output and the second converted output.Type: ApplicationFiled: May 4, 2017Publication date: December 7, 2017Inventors: Chan-Hsiang Weng, Tien-Yu Lo
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Patent number: 8957797Abstract: The present invention relates to an analog-to-digital converting circuit with temperature sensing and the electronic device thereof. The present invention uses a first impedance device to receive a reference voltage and produces an input current according to a temperature. An analog-to-digital converting unit is coupled to the first impedance device and produces a digital output signal according to the input current. Thereby, according to the present invention, by integrating the first impedance device into the analog-to-digital converting circuit, the circuit area and the power consumption can be lowered, which further reduces the cost and improves the accuracy of temperature sensing.Type: GrantFiled: June 17, 2013Date of Patent: February 17, 2015Assignees: Sitronix Technology Corp., National Taiwan UniversityInventors: Chan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin
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Publication number: 20140347198Abstract: The present invention relates to an analog-to-digital converting circuit with temperature sensing and the electronic device thereof. The present invention uses a first impedance device to receive a reference voltage and produces an input current according to a temperature. An analog-to-digital converting unit is coupled to the first impedance device and produces a digital output signal according to the input current. Thereby, according to the present invention, by integrating the first impedance device into the analog-to-digital converting circuit, the circuit area and the power consumption can be lowered, which further reduces the cost and improves the accuracy of temperature sensing.Type: ApplicationFiled: June 17, 2013Publication date: November 27, 2014Inventors: CHAN-HSIANG WENG, CHUN-KUAN WU, TSUNG-HSIEN LIN
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Patent number: 7535392Abstract: The invention provides a continuous-time delta sigma modulator. In one embodiment, the continuous-time delta sigma modulator comprises a series of integrators, a quantizer, and a loop delay compensation circuit. The integrators are coupled in series and generate an analog output signal according to an analog input signal. The quantizer quantizes the analog output signal according to a reference voltage to generate a digital output signal as the output of the continuous-time delta sigma modulator. The loop delay compensation circuit adjusts the reference voltage of the quantizer according to the digital output signal to compensate the continuous-time delta sigma modulator for a loop delay.Type: GrantFiled: October 4, 2007Date of Patent: May 19, 2009Assignees: Mediatek Inc., National Taiwan UniversityInventors: Chan-Hsiang Weng, Tsung-Hsien Lin
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Publication number: 20090091484Abstract: The invention provides a continuous-time delta sigma modulator. In one embodiment, the continuous-time delta sigma modulator comprises a series of integrators, a quantizer, and a loop delay compensation circuit. The integrators are coupled in series and generate an analog output signal according to an analog input signal. The quantizer quantizes the analog output signal according to a reference voltage to generate a digital output signal as the output of the continuous-time delta sigma modulator. The loop delay compensation circuit adjusts the reference voltage of the quantizer according to the digital output signal to compensate the continuous-time delta sigma modulator for a loop delay.Type: ApplicationFiled: October 4, 2007Publication date: April 9, 2009Applicants: MEDIATEK INC., NATIONAL TAIWAN UNIVERSITYInventors: Chan-Hsiang Weng, Tsung-Hsien Lin