Patents by Inventor Chan-Jen Kuo

Chan-Jen Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for forming a polysilicon layer in a polycide process flow
    Patent number: 6191019
    Abstract: A method for preventing void formation in a gate of a transistor formed in a substrate is disclosed. The method comprises: forming a gate oxide layer on the substrate; forming a polysilicon layer on the gate oxide layer; performing an ion implantation on the polysilicon layer, the ion implantation performed with a power approximately 30 KeV and a dosage about more than 1015 atoms/cm2; and forming a silicide layer on the polysilicon layer.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: February 20, 2001
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Cherng Liao, Jiunn-Liang Yu, Chan-Jen Kuo, Chi-San Wu, Yun-Chi Jiang
  • Method of planarizing memory cells
    Patent number: 5851874
    Abstract: A planarzation process is crucial for submicron VLSI or ULSI fabrication, The method of the present invention comprises forming a stacked capacitor contact on a substrate, forming a first dielectric layer on the capacitor contact. Next an etching process is performed to etchback the first dielectric layer. Finally, a second dielectric layer is formed on the first dielectric layer. A thermal reflowing may be also used to increase the planarization.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: December 22, 1998
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chan-Jen Kuo, Fu-Liang Yang