Abstract: A passenger conveyor (10) comprises a plurality of treads (16) interconnected to form an endless tread band (17), the passenger conveyor (10) comprising a chain and sprocket drive system including at least two drive sprockets (24a, 24b), each drive sprocket (24a, 24b) drivingly coupled to a respective drive chain (20a, 20b), each drive sprocket (24a, 24b) having a predetermined number of drive sprocket teeth (38a, 38b) positioned at a predetermined drive sprocket teeth pitch (?a, ?b) with respect to each other, wherein the drive sprockets (24a, 24b) are configured to rotate with the same angular velocity, but at a predetermined phase difference (?) with respect to each other.

Abstract: A drive chain band for a chain drive device having chain links and pins is provided. The drive chain band may include one or more drive bands, and a plurality of connectors disposed on the one or more drive bands. Each connector may have a toothed profile configured to directly receive and engage the pins.

Abstract: A turnaround mechanism for a passenger conveyor may include a turnaround track for facilitating a smooth transition of a plurality of pallets between a passenger side and a return side. Each of die plurality of pallets may have a front end portion engaged to the turnaround track. The turnaround mechanism may further include a track exchange mechanism having a track exchanger for transitioning the at least one roller of each of the plurality of pallets between the passenger and the return sides, each of the plurality of pallets generally maintaining its orientation during the transitioning.

Abstract: A drive chain band for a chain drive device having chain links and pins is provided. The drive chain band may include one or more drive bands, and a plurality of connectors disposed on the one or more drive bands. Each connector may have a toothed profile configured to directly receive and engage the pins.

Abstract: A turnaround mechanism for a passenger conveyor may include a turnaround track for facilitating a smooth transition of a plurality of pallets between a passenger side and a return side. Each of die plurality of pallets may have a front end portion engaged to the turnaround track. The turnaround mechanism may further include a track exchange mechanism having a track exchanger for transitioning the at least one roller of each of the plurality of pallets between the passenger and the return sides, each of the plurality of pallets generally maintaining its orientation during the transitioning.

Abstract: A method for constructing a map of a magnetic field includes acquiring the map information including the information on the internal or external structure of the building; measuring the information on the magnetic field, using the measurer's electronic device; and associating the information on the magnetic field with the map information based on the schedule information, wherein the schedule information is generated based on the structure information or a command made by the measurer.

Abstract: A method for measuring a location of a user terminal, using a magnetic field includes receiving information on a map of the magnetic field; acquiring a first measured value from a magnetic field sensor provided in the user terminal; acquiring a second measured value from another sensor provided in the user terminal and distinguished from the magnetic field sensor; and measuring a location of the user terminal based on the information on the map of the magnetic field, the first measured value and the second measured value.

Abstract: A system for braking an escalator or moving walkway includes a handrail and passenger support in registration with one another so as to move together. A braking tensioner selectively increases tension in the handrail during operation. The increased tension serves to frictionally brake the handrail and hence the passenger support. The braking tensioner may be located in any of various locations depending upon system design, and may be driven in any suitable manner, e.g., hydraulically, electrically, electromagnetically, and so on. Frictional wear on the handrail is reduced by the fact that the described braking system spreads the frictional load over a large area of the handrail, e.g., the many locations where the handrail contacts the underlying support throughout its length.

Abstract: A curvature-adjustable handrail length compensation device for an escalator or a moving walkway is provided. The device comprises a frame, handrail support mounted along a length of the frame, and springs mounted to the frame to elastically support the handrail support. Each handrail support includes a supporting rod movably mounted through the frame, a first supporting roller mounted to an end of the supporting rod to support the handrail, and a stopper formed at the other end of the supporting rod. The spring is provided between the frame and the first supporting roller, and biases the first supporting roller away from the frame.

Abstract: A curvature-adjustable handrail length compensation device for an escalator or a moving walkway is provided. The device comprises a frame, handrail support mounted along a length of the frame, and springs mounted to the frame to elastically support the handrail support. Each handrail support includes a supporting rod movably mounted through the frame, a first supporting roller mounted to an end of the supporting rod to support the handrail, and a stopper formed at the other end of the supporting rod. The spring is provided between the frame and the first supporting roller, and biases the first supporting roller away from the frame.

Abstract: The present invention relates to a system and method for virtual reality game. More particularly, the system exploits a terminal, a server, and network connecting the terminal and the server together such as internet. An exercise machine connected to the above terminal enables users in various terminals connected to the server to exercise appreciating virtual or real images and have a race each other with permitting the same load with a real racing course by converting a load in accordance with a load condition of synthetic image comprising the user's avatar transmitted from the server to the terminal and an image of a racing course.

Abstract: A virtual space search interface is provided to search a three-dimensional virtual space image by the visual angle of a virtual user immersed therein. The virtual space search interface engine interfaces the movement of the virtual user so as to adjust it with a mouse in such a way as the movement of a visual line of the body, displays an ICON which can adjust a three-dimensional motion with a mouse on the main image in which the search is made and enables the ICON to search a three-dimensional virtual space image by selecting an element of changes of a gaze, controlling changes of movement in horizon, its moving speed and 2-dimensional movement of neck. Consequently, movement is more free than the use of various ICONs. Since the user is well acquainted with the ICON which represents the body, the user knows what manipulation is good and when such manipulation can be executed so that a virtual space can be searched easily.

Abstract: A current control circuit capable of minimizing changes in an output high voltage VOH and an output low voltage VOL and quickly and accurately bringing a divided voltage to a steady state, and a packet-type semiconductor memory device including the current control circuit. The current control circuit includes a first differential amplification type buffer for transmitting the voltage of a first pad, that is, the output high voltage VOH, without change in response to a current control enable signal, a second differential amplification type buffer for transmitting the voltage of a second pad, that is, the output low voltage VOL, without change in response to the current control enable signal, and a voltage divider for dividing a voltage ranging between the voltage outputs of the first and second differential amplification buffers, and outputting the divided voltage.

Abstract: A semiconductor integrated circuit includes a plurality of signal wires and an array of capacitor-based memory cells. The capacitors of the memory cells are electrically coupled to a common voltage source node where a voltage source provides supply power to the array. Shield wires positioned proximal to the signal wires are electrically coupled to the common voltage source node. A shield capacitor may be provided between the signal wires and the common voltage source node to provide further noise suppression.

Abstract: The present invention is related to a system which is portable and attache the body of a trainee so that the trainee can practice navigating of a model airplane at an arbitrary location, contrary to the system of a large-sized airplane. According to an object of the present invention there is provided a trainee navigates a model airplane virtually by simulating a model airplane using a computer by combining the three-dimensional virtual image of a model airplane and the actual image of the training site by a computer.

Abstract: There is disclosed a parallel test circuit for a semiconductor memory device having a memory army with a plurality of memory cells and a plurality of comparators used for high-speed memory cell test, including a plurality of fist comparators performing first comparison with respect to data transmitted through a plurality of data output lines formed near memory blocks of the memory array; a plurality of second comparators coupled in common with each output terminal of the first comparators and performing second comparison with respect to output data of the first comparators; a multiplexer multiplexing output of the second comparator; first and second switches alternatively connected to an output terminal of the multiplexer; and a data output buffer coupled in common with output terminals of the first and second switches and buffering outputs of the first and second switches.

Abstract: A method for detecting an overvoltage signal applied to a semiconductor memory device address pin reduces stress on the device and simplifies the testing process by dividing the voltage of the overvoltage signal and comparing it to a reference voltage, thereby generating a difference signal. The difference signal is buffered by a drive stage which generates a test mode output signal that places the memory device in a test mode. An overvoltage detection circuit for implementing this method includes a comparison signal generator having a resistive voltage divider for dividing the overvoltage signal and generating a comparison signal. A differential amplifier compares the comparison signal to a reference signal from a reference signal generator. The differential amplifier generates a difference signal which is coupled to a drive stage which generates a test mode output signal. The comparison signal generator, the differential amplifier, and the drive stage can be enabled in response to a test mode enable signal.

Abstract: A fast data transmission circuit for a semiconductor memory minimizes voltage variations of a data transmission line without the use of a separate data transmission voltage. The data transmission circuit includes a pair of input nodes, a data transmission line pair, a pair of sensing nodes, a pair of output nodes, and a control electrode. Prior to data transmission, the output nodes are pulled up to a high voltage state, the data transmission line pair is pulled down to a low voltage state, and the sensing nodes are held between the high and low voltage states. When the control pulse is applied to the control electrode, the sensing node voltage levels are transferred to the data transmission line pair by the sensing voltage transfer circuit. When one input node is pulled to a low voltage state, a corresponding one voltage level on one transmission line is changed, causing a corresponding change of voltage at one of the sensing nodes.

Abstract: A boosting voltage level detector for a semiconductor memory device which utilizes a boosting voltage the level of which is higher than that of a power supply voltage, which includes a pull-up portion and a pull-down portion. In a preferred embodiment, the pull-up portion includes a PMOS transistor and a first NMOS transistor connected in series between the power supply voltage and an output node, and the pull-down portion includes second and third NMOS transistors connected in series between the output node and ground. The PMOS transistor has a gate electrode which is coupled to ground, and thus functions as a current source. The second NMOS transistor has a gate electrode which is coupled to a reference voltage, and thus functions as a resistor. The gate electrodes of the first and third NMOS transistors are commonly coupled to the boosting voltage. The detector further includes an inverter circuit coupled to the output node.

Abstract: A voltage boosting circuit for a semiconductor memory device has a clock generator for supplying a chip master clock determining an active state and a stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of the chip master clock is generated, and for generating a latch control signal a second delay time after the first state of the chip master clock is generated. A boosting voltage detector responds to the detector control signal and the latch control signal to generate a detecting signal indicative of a current state of a boosting voltage potential. First and second boosting voltage generators generate the boosting voltage potential, respectively operating in the stand-by state and active state in accordance with the detecting signal and delayed chip master clock signal.