Patents by Inventor Chan-Jong WOO
Chan-Jong WOO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11709777Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.Type: GrantFiled: October 4, 2021Date of Patent: July 25, 2023Assignee: SK hynix Inc.Inventors: Yong-Woo Lee, Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Jae-Jin Lee, Hun-Sam Jung, Chan-Jong Woo
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Publication number: 20220027279Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.Type: ApplicationFiled: October 4, 2021Publication date: January 27, 2022Inventors: Yong-Woo LEE, Min-Chang KIM, Chang-Hyun KIM, Do-Yun LEE, Jae-Jin LEE, Hun-Sam JUNG, Chan-Jong WOO
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Patent number: 11194479Abstract: A memory system includes a memory controller; a first memory module, the first memory module including first volatile memory devices; a second memory module, the second memory module including nonvolatile memory devices; a data bus for transmitting data between the memory controller and the first memory module and between the memory controller and the second memory module; a first control bus for transmitting first control signals between the memory controller and the first memory module and between the memory controller and the second memory module; a second control bus for transmitting second control signals between the memory controller and the first memory module; and a third control bus for transmitting third control signals between the memory controller and the second memory module, wherein, in a backup operation, the second control bus and the third control bus are electrically coupled.Type: GrantFiled: November 11, 2019Date of Patent: December 7, 2021Assignee: SK hynix Inc.Inventor: Chan-Jong Woo
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Patent number: 11138120Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.Type: GrantFiled: February 24, 2020Date of Patent: October 5, 2021Assignee: SK hynix Inc.Inventors: Yong-Woo Lee, Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Jae-Jin Lee, Hun-Sam Jung, Chan-Jong Woo
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Publication number: 20200192804Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.Type: ApplicationFiled: February 24, 2020Publication date: June 18, 2020Inventors: Yong-Woo LEE, Min-Chang KIM, Chang-Hyun KIM, Do-Yun LEE, Jae-Jin LEE, Hun-Sam JUNG, Chan-Jong WOO
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Publication number: 20200081632Abstract: A memory system includes a memory controller; a first memory module, the first memory module including first volatile memory devices; a second memory module, the second memory module including nonvolatile memory devices; a data bus for transmitting data between the memory controller and the first memory module and between the memory controller and the second memory module; a first control bus for transmitting first control signals between the memory controller and the first memory module and between the memory controller and the second memory module; a second control bus for transmitting second control signals between the memory controller and the first memory module; and a third control bus for transmitting third control signals between the memory controller and the second memory module, wherein, in a backup operation, the second control bus and the third control bus are electrically coupled.Type: ApplicationFiled: November 11, 2019Publication date: March 12, 2020Inventor: Chan-Jong Woo
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Patent number: 10474378Abstract: A memory system includes a memory controller; a first memory module, the first memory module including first volatile memory devices; a second memory module, the second memory module including nonvolatile memory devices; a data bus for transmitting data between the memory controller and the first memory module and between the memory controller and the second memory module; a first control bus for transmitting first control signals between the memory controller and the first memory module and between the memory controller and the second memory module; a second control bus for transmitting second control signals between the memory controller and the first memory module; and a third control bus for transmitting third control signals between the memory controller and the second memory module, wherein, in a backup operation, the second control bus and the third control bus are electrically coupled.Type: GrantFiled: August 7, 2017Date of Patent: November 12, 2019Assignee: SK hynix Inc.Inventor: Chan-Jong Woo
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Patent number: 10146709Abstract: A method for operating a memory system including a memory controller and a memory module, the method includes: by the memory controller, applying a read command to the memory module; by the memory module, determining whether the memory module is able to transfer the read data to the memory controller during a regulated section; by the memory module, notifying the memory controller by using a data strobe signal that the memory module is not able to transfer the read data to the memory controller during the regulated section; by the memory controller, applying a status check-out command to the memory module in response to the notification for checking out a status of the memory module; and by the memory module, transferring status information of the memory module to the memory controller in response to the status check-out command.Type: GrantFiled: August 2, 2017Date of Patent: December 4, 2018Assignee: SK Hynix Inc.Inventor: Chan-Jong Woo
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Publication number: 20180181325Abstract: A memory system includes a memory controller; a first memory module, the first memory module including first volatile memory devices; a second memory module, the second memory module including nonvolatile memory devices; a data bus for transmitting data between the memory controller and the first memory module and between the memory controller and the second memory module; a first control bus for transmitting first control signals between the memory controller and the first memory module and between the memory controller and the second memory module; a second control bus for transmitting second control signals between the memory controller and the first memory module; and a third control bus for transmitting third control signals between the memory controller and the second memory module, wherein, in a backup operation, the second control bus and the third control bus are electrically coupled.Type: ApplicationFiled: August 7, 2017Publication date: June 28, 2018Inventor: Chan-Jong WOO
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Publication number: 20180173650Abstract: A method for operating a memory system including a memory controller and a memory mudule, the method includes: by the memory controller, applying a read command to the memory module; by the memory module, determining whether the memory module is able to transfer the read data to the memory controller during a regulated section; by the memory module, notifying the memory controller by using a data strobe signal that the memory module is not able to transfer the read data to the memory controller during the regulated section; by the memory controller, applying a status check-out command to the memory module in response to the notification for checking out a status of the memory module; and by the memory module, transferring status information of the memory module to the memory controller in response to the status check-out command.Type: ApplicationFiled: August 2, 2017Publication date: June 21, 2018Inventor: Chan-Jong WOO