Abstract: A memory device includes a cell string comprising a plurality of memory cells and a page buffer coupled to the cell string. The page buffer includes a latch with cross-coupled transistors. Data transferred from the cell string to the page buffer is input to gates of plural transistors included in the page buffer.

Abstract: A signal transmission circuit comprising: a first data transmission circuit configured to output, through a first data output node thereof and in response to a first operation clock applied to a first clock input node thereof, first output data obtained by sensing and amplifying a first input data pair applied to a first differential input node pair thereof, a clock transmission circuit configured to output through a second data output node thereof, a second operation clock generated in response to the first operation clock applied to a second clock input node thereof while a power supply voltage and a ground voltage are applied to a second differential input node pair thereof, and a first data output circuit configured to output the first output data in synchronization with the second operation clock, wherein the first data transmission circuit is modeled on the clock transmission circuit.

Abstract: A memory system comprising a first memory device configured to compress, into first compression data, data read from a first memory region included therein, and output the first compression data through first selection lines among first output lines in response to a first clock, a second memory device configured to compress, into second compression data, data read from a second memory region included therein, and output the second compression data through second selection lines among second output lines in response to a second clock; and a first parallel transmission unit configured to simultaneously connect the first and second selection lines to third output lines, select, as a selection clock, one having a lagging phase to the other between the first clock and the second clock, and transmit the first and second compression data in parallel through the third output lines in response to the selection clock.

Abstract: A calibration device is coupled to a communication line shared by plural devices. The calibration device is configured to perform an iterative eye width scanning by adjusting a set voltage level by a preset level from a first voltage level to a reference center voltage level, wherein the first voltage level corresponds to a cross point where values of signals or data, which are transmitted via the communication lines, are changed in different directions; and determine, as a zero crossing for the signals or the data, a voltage level corresponding to a largest value among a plurality of eye widths obtained through the iterative eye width scanning.

Abstract: A test circuit of a semiconductor apparatus includes a first resistor, a second resistor and a feed-back loop circuit. The first resistor is coupled between a pad and a test element. The second resistor is coupled to the first resistor in a parallel manner. The feed-back loop circuit is configured to feed a result back to the second resistor, the result being one of comparing a first voltage and a second voltage with each other, the first voltage and the second voltage being applied respectively to the first resistor and the second resistor.

Abstract: A leakage current detection circuit includes: a mirror circuit configured to copy a leakage current flowing through a node and generate a copy current in a copy node; an oscillation circuit including a charge storage unit, the oscillation circuit being connected to the copy node, charged with the copy current, and configured to generate an oscillation signal by charging and discharging the charge storage unit; and a calculation circuit configured to calculate an amount of the leakage current based on the oscillation signal.

Abstract: A power circuit includes a plurality of regulators and a plurality of in-rush current controllers. The plurality of regulators is coupled to an external power voltage and configured to adjust a level of an input voltage to generate a plurality of internal power voltages. The plurality of in-rush current controllers is configured to provide the input voltage to the plurality of regulators, the input voltage corresponding to an increasement voltage. The increasement voltage has a level rising at a preset rate until the plurality of internal power voltages all reach a target level.

Abstract: A bandgap reference circuit includes a plurality of current sources including different temperature coefficients, a first trimmer, and a mixer. The first trimmer adjusts current amounts for a plurality of currents, which are individually output from each of the plurality of current sources, to be equal to each other. The mixer adjusts an aggregate ratio and combines the plurality of currents based on the aggregate ratio.

Abstract: A bandgap reference circuit includes a plurality of current sources including different temperature coefficients, a first trimmer, and a mixer, The first trimmer adjusts current amounts for a plurality of currents, which are individually output from each of the plurality of current sources, to be equal to each other. The mixer adjusts an aggregate ratio and combines the plurality of currents based on the aggregate ratio.

Abstract: The present disclosure relates to a semiconductor system including a semiconductor device and a controller. The semiconductor device outputs a temperature code corresponding to an internal temperature thereof. The controller controls, based on the temperature code, the semiconductor device to set a temperature measurement mode among at least two temperature measurement modes having different temperature measurement periods and to measure the internal temperature in the set temperature measurement mode.

Abstract: An internal voltage generation circuit comprising: a first voltage generator buffers a first reference voltage from a first to a second time point and integrates the first reference voltage after the second time point to generate a first initial voltage, a divider outputs a second initial voltage by dividing the first initial voltage from the first to the second time point and to outputs the first initial voltage as the second initial voltage after the second time point, a selector selects and output the second initial voltage or a second reference voltage based on a comparison of level of a feedback voltage and the second reference voltage, and a second voltage generator generates an internal voltage depending on a result of comparing levels of an output voltage of the selector and the feedback voltage, and to generates the feedback voltage by dividing the internal voltage.

Abstract: The present disclosure relates to an electronic device. An analog-digital converter includes an input voltage provider configured to output the input voltage during a plurality of stages, a comparator configured to output a comparison result between the input voltage and one of a plurality of comparison reference voltages, a successive approximation register configured to output at least one bit among the plurality of bits of digital data based on the comparison result, and a digital-analog converter configured to provide the comparator with one comparison reference voltage among the plurality of the comparison reference voltages based on the at least one bit, wherein the digital-analog converter includes a plurality of transistors that are coupled in parallel with each other, the digital-analog converter configured to selectively receive a plurality of reference voltages to generate the one comparison reference voltage.

Abstract: The present disclosure relates to an electronic device. An analog-digital converter includes an input voltage provider configured to output the input voltage during a plurality of stages, a comparator configured to output a comparison result between the input voltage and one of a plurality of comparison reference voltages, a successive approximation register configured to output at least one bit among the plurality of bits of digital data based on the comparison result, and a digital-analog converter configured to provide the comparator with one comparison reference voltage among the plurality of the comparison reference voltages based on the at least one bit, wherein the digital-analog converter includes a plurality of transistors that are coupled in parallel with each other, the digital-analog converter configured to selectively receive a plurality of reference voltages to generate the one comparison reference voltage.

Abstract: Provided is a digital filter that is configured to generate a first integration signal by integrating data groups, which are generated by sampling sample data within a first time period that overlaps with another time period, configured to generate a second integration signal by integrating data groups, which are generated by sampling the sample data within a second time period that is included in the first time period, the first time period and the second time period overlapping with one another, and configured to output a difference between the first and second integration signals as digital data. The first integration signal is generated during a third time period that is included in the first time period.

Abstract: Provided is a digital filter that is configured to generate a first integration signal by integrating data groups, which are generated by sampling sample data within a first time period that overlaps with another time period, configured to generate a second integration signal by integrating data groups, which are generated by sampling the sample data within a second time period that is included in the first time period, the first time period and the second time period overlapping with one another, and configured to output a difference between the first and second integration signals as digital data. The first integration signal is generated during a third time period that is included in the first time period.

Abstract: The present disclosure relates to a semiconductor system includes a semiconductor device and a controller. The semiconductor device outputs a temperature code corresponding to an internal temperature thereof. The controller controls, based on the temperature code, the semiconductor device to set a temperature measurement mode among at least two temperature measurement modes having different temperature measurement periods and to measure the internal temperature in the set temperature measurement mode.

Abstract: Provided herein may be a temperature sensing circuit and a semiconductor device having the same. The temperature sensing circuit may include an analog voltage generation circuit configured to convert a temperature into a voltage and output a temperature voltage, an analog-digital converter configured to convert the temperature voltage into a digital code, and a compensation circuit configured to adjust the digital code and then output an operation code to remove noise from the temperature voltage.

Abstract: A voltage trimming circuit may include: a resistor array configured to divide a first voltage at different division ratios through output nodes, output the divided voltages, and change a resistance value based on one or more voltage level control signals; and a multiplexer configured to select one voltage level from the output nodes based on the remainder of the voltage level control signals and output a voltage level of the selected node as an output voltage.

Abstract: Provided herein may be a temperature sensing circuit and a semiconductor device having the same. The temperature sensing circuit may include an analog voltage generation circuit configured to convert a temperature into a voltage and output a temperature voltage, an analog-digital converter configured to convert the temperature voltage into a digital code, and a compensation circuit configured to adjust the digital code and then output an operation code to remove noise from the temperature voltage.