Patents by Inventor Chan Kim Lee
Chan Kim Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11946031Abstract: Provided is yarn for a cell culture scaffold. The yarn for a cell culture scaffold according to an exemplary embodiment of the present invention includes slitting yarn produced by cutting a compressed nanofiber web to a predetermined width. Accordingly, by creating microenvironments suitable for migration, proliferation and differentiation of cells, cell viability may be enhanced and cells may be three-dimensionally proliferated. In addition, a scaffold according to the present invention has a mechanical strength sufficient for prevention of disruption of the scaffold which occurs during cell culture, such that cells may be stably proliferated. Further, the scaffold according to the present invention uses slitting yarn formed of the compressed nanofiber web, thereby having pores with various sizes, and therefore cell proliferation and cell viability may be enhanced by creation of an extracellular matrix-like environment.Type: GrantFiled: June 13, 2017Date of Patent: April 2, 2024Assignee: AMOGREENTECH CO., LTD.Inventors: In Yong Seo, Seon Ho Jang, Chan Kim, Seoung Hoon Lee, Song Hee Koo
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Publication number: 20240071948Abstract: A semiconductor package is provided including: a package substrate with a top surface, wherein the top surface extends to a peripheral side surface of the package substrate; a stiffener with a lateral portion and a basket portion, wherein the lateral portion is positioned over the top surface of the package substrate and the basket portion overhangs from the top surface of the package substrate adjacent to the peripheral side surface of the package substrate; at least one semiconductor die positioned in the basket portion of the stiffener; and at least one wire attached to the at least one semiconductor die and extending out of the basket portion of the stiffener.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Jiun Hann SIR, Eng Huat GOH, Poh Boon KHOO, Nurul Khalidah YUSOP, Saw Beng TEOH, Chan Kim LEE
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Publication number: 20240006399Abstract: An electronic device includes a package substrate; a memory integrated circuit (IC) mounted on the package substrate; a mold layer including one or more chiplets and a base IC die within the mold layer, the one or more chiplets arranged on the base IC die; a top chiplet mounted on a surface of the mold layer, wherein a combined height of the mold layer and the top chiplet substantially matches a height of the memory IC; and a heat spreader having a uniform surface contacting the memory IC and the top chiplet.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Seok Ling Lim, Chan Kim Lee, Eng Huat Goh, Jenny Shio Yin Ong, Tin Poay Chuah
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Publication number: 20230397333Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core. In an embodiment, the core comprises a first sub-core layer and a second sub-core layer. In an embodiment, a via is provided through the first sub-core layer and the second sub-core layer. In an embodiment, the via comprises a first hourglass shape in the first sub-core layer and a second hourglass shape in the second sub-core layer. In an embodiment, a front-side buildup layer is over the core and a backside buildup layer is under the core.Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Inventors: Eng Huat GOH, Chee Kheong YOON, Telesphor KAMGAING, Jooi Wah WONG, Min Suet LIM, Kavitha NAGARAJAN, Chan Kim LEE, Chu Aun LIM
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Patent number: 11482481Abstract: An electronic device is disclosed. In one example, the electronic device includes a circuit board comprising a recess a package in the recess, a semiconductor die coupled to the first side of the package, and a bridge extending from the first side of the package to the circuit board wherein the bridge electrically couples the package to the circuit board.Type: GrantFiled: May 29, 2020Date of Patent: October 25, 2022Assignee: Intel CorporationInventors: Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi, Lee Fueng Yap, Chan Kim Lee
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Patent number: 11096284Abstract: A semiconductor device and associated methods are disclosed. In one example, a processor die is coupled to a first side of a package substrate, and a memory die coupled to a second side of the package substrate. A system accelerator die is further coupled to the package substrate. In selected examples, the system accelerator die provides performance improvements, such as higher cached memory speed and/or higher memory bandwidth.Type: GrantFiled: June 25, 2019Date of Patent: August 17, 2021Assignee: Intel CorporationInventors: Wee Hoe, Chan Kim Lee, Chee Chun Yee, Mooi Ling Chang, Siang Yeong Tan, Say Thong Tony Tan
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Publication number: 20210098350Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a circuit board comprising a recess a package in the recess, a semiconductor die coupled to the first side of the package, and a bridge extending from the first side of the package to the circuit board wherein the bridge electrically couples the package to the circuit board.Type: ApplicationFiled: May 29, 2020Publication date: April 1, 2021Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi, Lee Fueng Yap, Chan Kim Lee
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Publication number: 20200107444Abstract: A semiconductor device and associated methods are disclosed. In one example, a processor die is coupled to a first side of a package substrate, and a memory die coupled to a second side of the package substrate. A system accelerator die is further coupled to the package substrate. In selected examples, the system accelerator die provides performance improvements, such as higher cached memory speed and/or higher memory bandwidth.Type: ApplicationFiled: June 25, 2019Publication date: April 2, 2020Inventors: Wee Hoe, CHAN KIM LEE, CHEE CHUN YEE, Mooi Ling Chang, Siang Yeong Tan, Say Thong Tony Tan
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Patent number: 9543244Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.Type: GrantFiled: November 17, 2014Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Chung Peng Jackson Kong, Chang-Tsung Fu, Telesphor Kamgaing, Chan Kim Lee, Ping Ping Ooi
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Publication number: 20150069629Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.Type: ApplicationFiled: November 17, 2014Publication date: March 12, 2015Inventors: Chung Peng Jackson KONG, Chang-Tsung Fu, Telesphor Kamgaing, Chan Kim Lee, Ping Ping Ooi
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Patent number: 8890302Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.Type: GrantFiled: June 29, 2012Date of Patent: November 18, 2014Assignee: Intel CorporationInventors: Chung Peng (Jackson) Kong, Chang-Tsung Fu, Telesphor Kamgaing, Chan Kim Lee, Ping Ping Ooi
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Publication number: 20140001643Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Inventors: Chung Peng (Jackson) KONG, Chang-Tsung FU, Telesphor KAMGAING, Chan Kim LEE, Ping Ping OOI
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Publication number: 20080067665Abstract: In one embodiment, the invention may include a semiconductor package substrate with a plated-through hole (PTH) via. One or more conduits for transmitting signals can be located in the PTH via. The PTH via may shield the signals in the conduits from environmental noise (e.g., EMI). Other embodiments are described and claimed.Type: ApplicationFiled: September 20, 2006Publication date: March 20, 2008Inventors: Azniza Binti Abd Aziz, Chan Kim Lee, Kuen Yew Lam
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Patent number: D759029Type: GrantFiled: May 21, 2015Date of Patent: June 14, 2016Assignee: Intel CorporationInventors: Howe Yin Loo, Greg A. La Tour, Chan Kim Lee, Bok Eng Cheah, Khai Ern See, Han Kung Chua, Chow Soon Lim, Choy Mei Yeow