Abstract: Provided is a method for manufacturing yarn for a cell culture scaffold. The method includes: (1) preparing a ply yarn by twisting a plurality of fiber strands; and (2) partially untwisting at least one part of the ply yarn in the longitudinal direction in a direction opposite to a direction in which the fiber strands are twisted to implement a space which is formed by spacing apart of the adjacent fiber strands within the untwisted part. The fiber strand is spun yarn, filament yarn or slitting yarn.

Abstract: A thermally adhesive fiber web implemented by including the steps of: (1) preparing respectively a first spinning solution in which a support component and a second spinning solution in which a thermally adhesive component; (2) performing electrospinning such that the first spinning solution is discharged to a portion of the end surface of a discharge port and the second spinning solution is discharged to the remaining portion, thereby accumulating side-by-side type thermally adhesive composite fibers having a diameter of less than 1 ?m; and (3) applying heat to the accumulated side-by-side type thermally adhesive composite fibers. The thermally adhesive fiber web enables easy interfacial bonding to a heterogeneous material with a different material and structural specification and prevents pores formed in an initial stage from being closed during thermal bonding.

Abstract: Disclosed herein are a catalyst for low-temperature carbon monoxide purification, a method for manufacturing the same, and a method for purifying carbon monoxide using the same. The catalyst comprises a metal oxide carrier; a transition metal oxide primarily supported on the carrier, and ruthenium secondarily supported on a carrier carrying the transition metal oxide. The catalyst provides an effect capable of purifying carbon monoxide contained in a hydrogen gas at a low temperature.

Abstract: A computing system including a processor in communication with a memory with instructions stored thereon is described. The instructions, when executed by the processor, cause the processor to receive application data associated with a user and a first offering, identify whether the user qualifies for the first offering, and compare the application data with stored parameters associated with a second offering. The instructions further cause the processor to, based on the application data satisfying the stored parameters, cause display of a first display area and a second display area at a graphical user interface (GUI) of a user computing device wherein the first display area includes a confirmation indicating whether the user qualifies for the first offering, and the second display area includes a description of the second offering, receive an input indicating acceptance of the second offering, and initiate activation of credentials associated with the second offering.

Abstract: A semiconductor package is provided including: a package substrate with a top surface, wherein the top surface extends to a peripheral side surface of the package substrate; a stiffener with a lateral portion and a basket portion, wherein the lateral portion is positioned over the top surface of the package substrate and the basket portion overhangs from the top surface of the package substrate adjacent to the peripheral side surface of the package substrate; at least one semiconductor die positioned in the basket portion of the stiffener; and at least one wire attached to the at least one semiconductor die and extending out of the basket portion of the stiffener.

Abstract: An electronic device includes a package substrate; a memory integrated circuit (IC) mounted on the package substrate; a mold layer including one or more chiplets and a base IC die within the mold layer, the one or more chiplets arranged on the base IC die; a top chiplet mounted on a surface of the mold layer, wherein a combined height of the mold layer and the top chiplet substantially matches a height of the memory IC; and a heat spreader having a uniform surface contacting the memory IC and the top chiplet.

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core. In an embodiment, the core comprises a first sub-core layer and a second sub-core layer. In an embodiment, a via is provided through the first sub-core layer and the second sub-core layer. In an embodiment, the via comprises a first hourglass shape in the first sub-core layer and a second hourglass shape in the second sub-core layer. In an embodiment, a front-side buildup layer is over the core and a backside buildup layer is under the core.

Abstract: An electronic device is disclosed. In one example, the electronic device includes a circuit board comprising a recess a package in the recess, a semiconductor die coupled to the first side of the package, and a bridge extending from the first side of the package to the circuit board wherein the bridge electrically couples the package to the circuit board.

Abstract: A semiconductor device and associated methods are disclosed. In one example, a processor die is coupled to a first side of a package substrate, and a memory die coupled to a second side of the package substrate. A system accelerator die is further coupled to the package substrate. In selected examples, the system accelerator die provides performance improvements, such as higher cached memory speed and/or higher memory bandwidth.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a circuit board comprising a recess a package in the recess, a semiconductor die coupled to the first side of the package, and a bridge extending from the first side of the package to the circuit board wherein the bridge electrically couples the package to the circuit board.

Abstract: A semiconductor device and associated methods are disclosed. In one example, a processor die is coupled to a first side of a package substrate, and a memory die coupled to a second side of the package substrate. A system accelerator die is further coupled to the package substrate. In selected examples, the system accelerator die provides performance improvements, such as higher cached memory speed and/or higher memory bandwidth.

Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.

Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.

Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.

Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.

Abstract: In one embodiment, the invention may include a semiconductor package substrate with a plated-through hole (PTH) via. One or more conduits for transmitting signals can be located in the PTH via. The PTH via may shield the signals in the conduits from environmental noise (e.g., EMI). Other embodiments are described and claimed.