Abstract: A power die package includes a power die having a plurality of bond pads at an upper surface of the power die. The package further includes a plurality of contact structures. A contact structure includes: a bond wire bonded to one of the plurality of bond pads and folded back to the bond pad to form a closed loop, or at least three bumps laterally spaced from one another and disposed on one or more bond pads; and a continuous longitudinally extended electrically conductive element connected to the at least three bumps in at least three contact positions. The conductive element bends away from the power die between pairs of consecutive contact positions. The package further includes a mold compound partially encapsulating the contact structure. The mold compound includes an outer surface facing away from the power die. The contact structure is partially exposed at the outer surface.

Abstract: A chip package includes a chip with at least one contact pad, a contact structure formed from at least one continuous longitudinally extended electrically conductive element by attaching the conductive element to the contact pad in at least three contact positions, wherein the conductive element bends away from the contact pad between pairs of consecutive contact positions, and an encapsulation partially encapsulating the contact structure, wherein the encapsulation includes an outer surface facing away from the chip, and wherein the contact structure is partially exposed at the outer surface.

Abstract: A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.

Abstract: A method includes providing a lead frame including a die pad and a plurality of leads, providing a first semiconductor die that includes a first load terminal disposed on a main surface, providing a second semiconductor die that includes a plurality of I/O terminals disposed on a main surface, mounting the first and second semiconductor dies on the lead frame such that the main surfaces of the first and second semiconductor dies face away from the die pad, forming an encapsulant body of mold compound that encapsulates the first and second semiconductor dies, forming a plurality of conductive tracks on an upper surface of the encapsulant body that electrically connect at least some of the I/O terminals to a first group of the leads, and forming a metal pad on the upper surface of the encapsulant body that electrically connects the first load terminal to a second lead.

Abstract: A chip package includes a chip with at least one contact pad, a contact structure formed from at least one continuous longitudinally extended electrically conductive element by attaching the conductive element to the contact pad in at least three contact positions, wherein the conductive element bends away from the contact pad between pairs of consecutive contact positions, and an encapsulation partially encapsulating the contact structure, wherein the encapsulation includes an outer surface facing away from the chip, and wherein the contact structure is partially exposed at the outer surface.

Abstract: A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.

Abstract: A method of forming a semiconductor package includes providing a metal baseplate including a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.

Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.

Abstract: The method for fabricating an electrical module is disclosed. In one example, the method includes providing a bottom unit comprising a plateable encapsulant. Selective areas of the bottom unit are activated thereby turning them into electrically conductive regions. At least one electrical device comprising external contact elements is provided. The method includes placing the electrical device on the bottom unit so that the external contact elements are positioned above at least a first subset of the electrically conductive regions, and performing a plating process on the electrically conductive regions for generating plated regions and for electrically connecting the external contact elements with at least a first subset of the plated regions.

Abstract: A package includes a dielectric carrier, an electronic component mounted on the dielectric carrier, and an encapsulant encapsulating at least part of the dielectric carrier and the electronic component. Corresponding methods of manufacturing the package are also described.

Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.

Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.

Abstract: A packaged semiconductor device includes a carrier having a die attach surface, a semiconductor die mounted on the die attach surface and comprising first and second conductive terminals disposed on an upper side, a first clip that extends over the semiconductor die and is electrically connected to the first conductive terminal, a second clip that extends over the semiconductor die and is electrically connected to the second conductive terminal, and an electrically insulating encapsulant body that encapsulates the semiconductor die. An outer end of the first clip is exposed from the encapsulant body and provides a point of external electrical contact for the first conductive terminal. An outer end of the second clip is exposed from the same or a different side face of the encapsulant body as the first clip and provides a point of external electrical contact for the second conductive terminal.

Abstract: A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.

Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.

Abstract: A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.

Abstract: A packaged semiconductor device includes a carrier having a die attach surface, a semiconductor die mounted on the die attach surface and comprising first and second conductive terminals disposed on an upper side, a first clip that extends over the semiconductor die and is electrically connected to the first conductive terminal, a second clip that extends over the semiconductor die and is electrically connected to the second conductive terminal, and an electrically insulating encapsulant body that encapsulates the semiconductor die. An outer end of the first clip is exposed from the encapsulant body and provides a point of external electrical contact for the first conductive terminal. An outer end of the second clip is exposed from the same or a different side face of the encapsulant body as the first clip and provides a point of external electrical contact for the second conductive terminal.

Abstract: A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.

Abstract: A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.

Abstract: A lead frame includes a die paddle, a first lead, and a U-notch coupling the die paddle to the first lead. The U-notch extends from the die paddle and the first lead. The U-notch is configured to be removed to electrically isolate the first lead from the die paddle.