Patents by Inventor Chan-Liang Wu
Chan-Liang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8912671Abstract: A semiconductor device including a substrate and at least one alignment mark disposed on the substrate and having at least one hollow pattern. Therefore, the identification rate of the alignment mark can be high by the hollow pattern.Type: GrantFiled: May 16, 2013Date of Patent: December 16, 2014Assignees: Himax Technologies Limited, Himax Semiconductor, Inc.Inventors: Po-Yang Tsai, Chan-Liang Wu
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Publication number: 20140339714Abstract: A semiconductor device including a substrate and at least one alignment mark disposed on the substrate and having at least one hollow pattern. Therefore, the identification rate of the alignment mark can be high by the hollow pattern.Type: ApplicationFiled: May 16, 2013Publication date: November 20, 2014Applicants: Himax Semiconductor, Inc., HIMAX TECHNOLOGIES LIMITEDInventors: Po-Yang Tsai, Chan-Liang Wu
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Patent number: 8751987Abstract: A method of resistor matching in analog integrated circuit layout is disclosed. Shapes of mismatching resistor blocks are analyzed to obtain geometrical information for deforming the mismatching resistor blocks. The mismatching resistor blocks are deformed into centrosymmetrical blocks according to the obtained geometrical information, each mismatching resistor block being decomposed to a plurality of unit-resistors. The unit-resistors are placed into matching resistor blocks to return a resulting layout with improved matching quality by reducing centroid offset between a centroid of the unit-resistors and a centroid of the matching resistor block.Type: GrantFiled: July 12, 2012Date of Patent: June 10, 2014Assignee: Oryx Holdings Pty Ltd.Inventors: Tsung-Yi Ho, Sheng-Jhih Jiang, Chan-Liang Wu
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Patent number: 8726214Abstract: A floorplanning method for an analog integrated circuit layout is disclosed. A first-type block is defined as a movable and deformable block with rectangle constraint, and a second-type block is defined as a fixed-size block without rectangle constraint. Each block in the floorplan is classified to the first-type or the second-type block. In a shape determination stage, a target shape is determined among candidates of the first-type block, the first-type block accordingly being modified to the target shape, resulting in at least one overlap in the floorplan. In an overlap elimination stage, neighboring blocks of each said overlap are analyzed, the overlap being then eliminated by utilizing surrounding space, resulting in unused space in the floorplan. In an enlargement stage, the unused space is utilized for enlarging the first-type block.Type: GrantFiled: July 2, 2012Date of Patent: May 13, 2014Assignees: NCKU Research and Development Foundation, Himax Technologies, Ltd.Inventors: Tsung-Yi Ho, Sheng-Jhih Jiang, Chan-Liang Wu
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Publication number: 20130283226Abstract: A floorplanning method for an analog integrated circuit layout is disclosed. A first-type block is defined as a movable and deformable block with rectangle constraint, and a second-type block is defined as a fixed-size block without rectangle constraint. Each block in the floorplan is classified to the first-type or the second-type block. In a shape determination stage, a target shape is determined among candidates of the first-type block, the first-type block accordingly being modified to the target shape, resulting in at least one overlap in the floorplan. In an overlap elimination stage, neighboring blocks of each said overlap are analyzed, the overlap being then eliminated by utilizing surrounding space, resulting in unused space in the floorplan. In an enlargement stage, the unused space is utilized for enlarging the first-type block.Type: ApplicationFiled: July 2, 2012Publication date: October 24, 2013Applicants: HIMAX TECHNOLOGIES LIMITED, NCKU RESEARCH AND DEVELOPMENT FOUNDATIONInventors: Tsung-Yi Ho, Sheng-Jhih Jiang, Chan-Liang Wu
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Publication number: 20130145332Abstract: A method of resistor matching in analog integrated circuit layout is disclosed. Shapes of mismatching resistor blocks are analyzed to obtain geometrical information for deforming the mismatching resistor blocks. The mismatching resistor blocks are deformed into centrosymmetrical blocks according to the obtained geometrical information, each mismatching resistor block being decomposed to a plurality of unit-resistors. The unit-resistors are placed into matching resistor blocks to return a resulting layout with improved matching quality by reducing centroid offset between a centroid of the unit-resistors and a centroid of the matching resistor block.Type: ApplicationFiled: July 12, 2012Publication date: June 6, 2013Applicants: HIMAX TECHNOLOGIES LIMITED, NCKU RESEARCH AND DEVELOPMENT FOUNDATIONInventors: Tsung-Yi Ho, Sheng-Jhih Jiang, Chan-Liang Wu
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Publication number: 20100257495Abstract: A 3D-IC verification method is disclosed. Alignment mark(s), through-silicon via (TSV) and bump structure are defined on dummy layer(s) for each level of the 3D IC, followed by verifying chip(s), the alignment mark, the TSV and the bump structure for each level respectively. The dummy layers of the levels are extracted, and are then integrated. The integrated dummy layers of the 3D IC are then verified vertically.Type: ApplicationFiled: April 6, 2009Publication date: October 7, 2010Inventor: Chan-Liang Wu
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Publication number: 20090309169Abstract: A structure for preventing leakage of a semiconductor device is provided. The structure comprises a shielding line, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The shielding line is wider than the conductive line.Type: ApplicationFiled: August 21, 2009Publication date: December 17, 2009Applicant: HIMAX TECHNOLOGIES LIMITEDInventor: Chan-Liang Wu
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Patent number: 7598585Abstract: A structure for preventing leakage of a semiconductor device is provided. The structure comprises a conductive layer, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The conductive layer is wider than the conductive line.Type: GrantFiled: May 24, 2006Date of Patent: October 6, 2009Assignee: Himax Technologies LimitedInventor: Chan-Liang Wu
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Patent number: 7541274Abstract: An integrated circuit with a reduced pad bump area and the manufacturing method thereof are disclosed. The integrated circuit includes a semiconductor substrate, an interconnection layer, a passivation layer, and at least a bump. The semiconductor substrate has a semiconductor device thereon. The interconnection layer is disposed on the semiconductor substrate and topped with a top metal layer which at least includes a bonding pad and a conductive line. The passivation layer is disposed on the interconnection layer and has at least an opening to expose the bonding pad. The bump is disposed on the passivation layer to connect the bonding pad through the opening and is extended to a coverage area not directly over the bonding pad.Type: GrantFiled: October 23, 2006Date of Patent: June 2, 2009Assignee: Himax Technologies LimitedInventors: Chan-Liang Wu, Ming-Cheng Chiu, Chien-Pin Chen
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Patent number: 7514761Abstract: A triple operation voltage device including a first type substrate, a high voltage (HV) first type well, a second type well, a low voltage (LV) device well, and a middle voltage (MV) device well is provided. The HV first type well is disposed inside the first type substrate. The second type well is disposed inside the first type substrate to separate the HV first type well from the first type substrate. The LV device well and the MV device well are separately disposed inside the HV first type well by the separation of the HV first type well. The triple operation voltage device assists in reducing the space between the LV device well and the MV device well and improving the integration of integrated circuits.Type: GrantFiled: November 8, 2005Date of Patent: April 7, 2009Assignee: Himax Technologies, Inc.Inventors: Tz-Ian Hung, Ming-Cheng Chiu, Chan-Liang Wu
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Patent number: 7388266Abstract: A structure for preventing leakage of a high voltage device is provided. The structure comprises a conductive layer, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The conductive layer is wider than the conductive line.Type: GrantFiled: August 18, 2005Date of Patent: June 17, 2008Assignee: Himax Technologies LimitedInventor: Chan-Liang Wu
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Publication number: 20080093737Abstract: An integrated circuit with a reduced pad bump area and the manufacturing method thereof are disclosed. The integrated circuit includes a semiconductor substrate, an interconnection layer, a passivation layer, and at least a bump. The semiconductor substrate has a semiconductor device thereon. The interconnection layer is disposed on the semiconductor substrate and topped with a top metal layer which at least includes a bonding pad and a conductive line. The passivation layer is disposed on the interconnection layer and has at least an opening to expose the bonding pad. The bump is disposed on the passivation layer to connect the bonding pad through the opening and is extended to a coverage area not directly over the bonding pad.Type: ApplicationFiled: October 23, 2006Publication date: April 24, 2008Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Chan-Liang Wu, Ming-Cheng Chiu, Chien-Pin Chen
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Publication number: 20070102782Abstract: A triple operation voltage device including a first type substrate, a high voltage (HV) first type well, a second type well, a low voltage (LV) device well, and a middle voltage (MV) device well is provided. The HV first type well is disposed inside the first type substrate. The second type well is disposed inside the first type substrate to separate the HV first type well from the first type substrate. The LV device well and the MV device well are separately disposed inside the HV first type well by the separation of the HV first type well. The triple operation voltage device assists in reducing the space between the LV device well and the MV device well and improving the integration of integrated circuits.Type: ApplicationFiled: November 8, 2005Publication date: May 10, 2007Inventors: Tz-Ian Hung, Ming-Cheng Chiu, Chan-Liang Wu
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Publication number: 20060255430Abstract: A structure for preventing leakage of a semiconductor device is provided. The structure comprises a conductive layer, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The conductive layer is wider than the conductive line.Type: ApplicationFiled: May 24, 2006Publication date: November 16, 2006Applicant: HIMAX TECHNOLOGIES, INC.Inventor: CHAN-LIANG WU
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Publication number: 20060255429Abstract: A structure for preventing leakage of a high voltage device is provided. The structure comprises a conductive layer, for shielding the features beneath thereof, located under a conductive line which crosses over a region having high voltage device. The conductive layer is wider than the conductive line.Type: ApplicationFiled: August 18, 2005Publication date: November 16, 2006Applicant: HIMAX TECHNOLOGIES, INC.Inventor: Chan-Liang Wu