Abstract: A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Abstract: A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Abstract: A semiconductor device including a PCB including conductive patterns formed on at least one surface of the PCB, external connection terminals including at least one ground terminal and coupled to the conductive patterns, at least one semiconductor chip mounted on a surface of the PCB, and an ESD protection pattern being coupled to at least one of the least one ground terminal, the at least one ground terminal not being coupled to the conductive patterns. A semiconductor memory device, including a PCB, a memory chip mounted on a first surface of the PCB, external connection terminals formed on a second surface of the PCB, and a first ESD protection pattern being coupled to at least one ground terminal. A method of mitigating ESD in a semiconductor device, including mounting a chip on a PCB, forming conductive patterns on the PCB, and forming at least one ESD protection pattern on the PCB, the ESD protection pattern being connected to a ground terminal and not being coupled to the conductive patterns.

Abstract: A semiconductor package including at least one semiconductor chip and inner leads may be provided. The semiconductor package may include a semiconductor chip. A plurality of inner leads having upper surfaces and lower surfaces, may be electrically connected to the semiconductor chip, and may be spaced apart from the semiconductor chip. A molding resin may fix the semiconductor chip and the inner leads. The upper surfaces of the inner leads may be fixed to the molding resin, the lower surfaces of the inner leads may be exposed from the molding resin, and widths of the lower surfaces of the inner leads may be narrower than widths of the upper surfaces of the inner leads.

Abstract: A lead-exposed semiconductor device package may include a die pad; a semiconductor chip having bonding pads mounted on the die pad; a plurality of leads arranged to be adjacent to at least one edge of the die pad and to electrically connect external to the package; a locking member provided on the plurality of leads; bonding wires electrically connecting the bonding pads with the plurality of leads; and a molding material for sealing the semiconductor chip, the die pad, the plurality of leads, the locking member, and the bonding wires. The locking member may be configured to lock the plurality of leads to the molding material.

Abstract: A semiconductor device including a PCB including conductive patterns formed on at least one surface of the PCB, external connection terminals including at least one ground terminal and coupled to the conductive patterns, at least one semiconductor chip mounted on a surface of the PCB, and an ESD protection pattern being coupled to at least one of the least one ground terminal, the at least one ground terminal not being coupled to the conductive patterns. A semiconductor memory device, including a PCB, a memory chip mounted on a first surface of the PCB, external connection terminals formed on a second surface of the PCB, and a first ESD protection pattern being coupled to at least one ground terminal. A method of mitigating ESD in a semiconductor device, including mounting a chip on a PCB, forming conductive patterns on the PCB, and forming at least one ESD protection pattern on the PCB, the ESD protection pattern being connected to a ground terminal and not being coupled to the conductive patterns.

Abstract: A carrier for use in testing an unpackaged semiconductor chip includes a body having a cavity for receiving the chip, inner contact elements and conductors for contacting connection pads on the chip and electrically connecting them to connection elements on an outside surface of the carrier, and rotatable clamps for holding the chip in the cavity. The carriers are configured to enable them to engage and mate with conventionally packaged chip test sockets, thereby enabling their use with conventional automated chip handling and testing equipment, and hence, the production of known good devices on a mass production basis.