Patents by Inventor Chan Min Yu
Chan Min Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240073586Abstract: A two-way speaker includes: a frame having a space for accommodating parts; a yoke partitioning the space of the frame vertically and having a lower surface and a side wall; a first speaker unit disposed below the yoke and having a magnet, a top plate, a voice coil, and a diaphragm; a protector disposed below the first speaker unit and protecting the diaphragm; a second speaker unit disposed above the yoke and having a magnetic circuit and a flexible-printed coil membrane (F-PCM) diaphragm having a coil pattern formed on a polymer film; and a sound emission yoke attached to an upper surface of the second speaker unit.Type: ApplicationFiled: August 30, 2023Publication date: February 29, 2024Inventors: Chan Ho Jeong, Young Seok Noh, Byung Min Yu
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Patent number: 8637973Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.Type: GrantFiled: March 27, 2007Date of Patent: January 28, 2014Assignee: Micron Technology, Inc.Inventors: Eng Meow Koon, Low Siu Waf, Chan Min Yu, Chia Yong Poo, Ser Bok Leng, Zhou Wei
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Patent number: 8138617Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.Type: GrantFiled: August 30, 2004Date of Patent: March 20, 2012Assignee: Round Rock Research, LLCInventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Loo, Eng Meow Koon, Ser Bok Leng, Chua Swee Kwang, So Chee Chung, Ho Kwok Seng
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Patent number: 8115306Abstract: An apparatus comprises an integrated circuit die including a main body having a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer. The integrated circuit die also includes a bond pad on the main body, an edge contact at the peripheral edge surface and a line connecting the bond pad to the edge contact. The edge contact includes a bottom surface that substantially in the same plane as a surface of an encapsulant encasing the die. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: February 12, 2010Date of Patent: February 14, 2012Assignee: Round Rock Research, LLCInventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Lou, Eng Meow Koon, Ser Bok Leng, Chun Swee Kwang, So Chee Chung, Ho Kwok Song
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Publication number: 20100140794Abstract: An apparatus comprises an integrated circuit die including a main body having a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer. The integrated circuit die also includes a bond pad on the main body, an edge contact at the peripheral edge surface and a line connecting the bond pad to the edge contact. The edge contact includes a bottom surface that substantially in the same plane as a surface of an encapsulant encasing the die. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: February 12, 2010Publication date: June 10, 2010Inventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Lou, Eng Meow Koon, Ser Bok Leng, Chun Swee Kwang, So Chee Chung, Ho Kwok Song
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Patent number: 7675169Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.Type: GrantFiled: November 2, 2007Date of Patent: March 9, 2010Assignee: Micron Technology, Inc.Inventors: Chia Yong Poo, Boon Suan Jeung, Low Slu Waf, Chan Min Yu, Neo Yong Loo, Eng Meow Koon, Ser Bok Leng, Chua Swee Kwang, So Chee Chung, Hu Kwok Seng
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Patent number: 7358154Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.Type: GrantFiled: November 17, 2005Date of Patent: April 15, 2008Assignee: Micron Technology, Inc.Inventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Loo, Eng Meow Koon, Ser Bok Leng, Chua Swee Kwang, So Chee Chung, Ho Kwok Seng
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Patent number: 7285850Abstract: A support structure for a semiconductor device with peripherally disposed contacts includes a support substrate and at least one conductive column protruding from the support substrate. The at least one conductive column is configured to contact an outer connector on a peripheral edge of a semiconductor device that may be carried by the support structure. Optionally, the at least one conductive column may engage a feature of (e.g., a recess in) the peripherally disposed outer connector. The at least one conductive column may facilitate alignment of one or more semiconductor devices with the support substrate alignment of semiconductor devices relative to one another, or electrical connection between multiple semiconductor devices of other components.Type: GrantFiled: May 8, 2006Date of Patent: October 23, 2007Assignee: Micron Technology, Inc.Inventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Loo, Chua Swee Kwang
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Patent number: 7226809Abstract: A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.Type: GrantFiled: May 19, 2003Date of Patent: June 5, 2007Assignee: Micron Technology, Inc.Inventors: Chia Yong Poo, Boon Suan Jeung, Chua Swee Kwang, Low Siu Waf, Chan Min Yu, Neo Yong Loo
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Patent number: 7195957Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.Type: GrantFiled: August 19, 2004Date of Patent: March 27, 2007Assignee: Micron Technology, Inc.Inventors: Eng Meow Koon, Low Siu Waf, Chan Min Yu, Chia Yong Poo, Ser Bok Leng, Zhou Wei
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Patent number: 7170161Abstract: Methods of forming a semiconductor assembly are described which include a leadframe with leads having offset portions exposed at an outer surface of a material package to form a grid array. An electrically conductive compound, such as solder, may be disposed or formed on the exposed lead portions to form a grid array such as a ball grid array (“BGA”) or other similar array-type structure of dielectric conductive elements. The leads may have inner bond ends including a contact pad thermocompressively bonded to a bond pad of the semiconductor chip to enable electrical communication therewith and a lead section with increased flexibility to improve the thermocompressive bond. The inner bond ends may also be wirebonded to the bond pads.Type: GrantFiled: June 16, 2005Date of Patent: January 30, 2007Assignee: Micron Technology, Inc.Inventors: Chan Min Yu, Ser Bok Leng, Low Siu Waf, Chia Yong Poo, Eng Meow Koon
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Patent number: 7115984Abstract: A semiconductor device package is disclosed which is substantially die-sized with respect to each of the X, Y and Z axes. The package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the height of the peripheral edge. Each outer connector is formed by severing a conductive via that extends substantially through a substrate blank, such as a silicon wafer, at a street located adjacent to an outer periphery of the semiconductor device of the package. The outer connectors may include recesses that at least partially receive conductive columns protruding from a support substrate therefor. Assemblies may include the packages in stacked arrangement, without height-adding connectors.Type: GrantFiled: December 15, 2003Date of Patent: October 3, 2006Assignee: Micron Technology, Inc.Inventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Loo, Chua Swee Kwang
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Patent number: 6967127Abstract: Methods of forming a semiconductor assembly are described which include a leadframe with leads having offset portions exposed at an outer surface of a material package to form a grid array. An electrically conductive compound, such as solder, may be disposed or formed on the exposed lead portions to form a grid array such as a ball grid array (“BGA”) or other similar array-type structure of dielectric conductive elements. The leads may have inner bond ends including a contact pad thermocompressively bonded to a bond pad of the semiconductor chip to enable electrical communication therewith and a lead section with increased flexibility to improve the thermocompressive bond. The inner bond ends may also be wirebonded to the bond pads.Type: GrantFiled: April 24, 2003Date of Patent: November 22, 2005Assignee: Micron Technology, Inc.Inventors: Chan Min Yu, Ser Bok Leng, Low Siu Waf, Chia Yong Poo, Eng Meow Koon
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Patent number: 6894386Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.Type: GrantFiled: April 8, 2002Date of Patent: May 17, 2005Assignee: Micron Technology, Inc.Inventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Loo, Eng Meow Koon, Ser Bok Leng, Chua Swee Kwang, So Chee Chung, Ho Kwok Seng
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Patent number: 6836009Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.Type: GrantFiled: August 28, 2002Date of Patent: December 28, 2004Assignee: Micron Technology, Inc.Inventors: Eng Meow Koon, Low Siu Waf, Chan Min Yu, Chia Yong Poo, Ser Bok Leng, Zhou Wei
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Patent number: 6836008Abstract: A semiconductor assembly includes a leadframe with leads having offset portions exposed at an outer surface of a material package to form a grid array. An electrically conductive compound, such as solder, may be disposed or formed on the exposed lead portions to form a grid array such as a ball grid array (“BGA”) or other similar array-type structure of dielectric conductive elements. The leads may have inner bond ends including a contact pad thermocompressively bonded to a bond pad of the semiconductor chip to enable electrical communication therewith and a lead section with increased flexibility to improve the thermocompressive bond. The inner bond ends may also be wirebonded to the bond pads. Components for and methods of forming semiconductor assemblies are included.Type: GrantFiled: May 1, 2002Date of Patent: December 28, 2004Assignee: Micron Technology, Inc.Inventors: Chan Min Yu, Ser Bok Leng, Low Siu Waf, Chia Yong Poo, Eng Meow Koon
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Patent number: 6818977Abstract: A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.Type: GrantFiled: July 17, 2002Date of Patent: November 16, 2004Assignee: Micron Technology, Inc.Inventors: Chia Yong Poo, Boon Suan Jeung, Chua Swee Kwang, Low Siu Waf, Chan Min Yu, Neo Yong Loo
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Publication number: 20040124523Abstract: A semiconductor device package is disclosed which is substantially die-sized with respect to each of the X, Y and Z axes. The package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the height of the peripheral edge. Each outer connector is formed by severing a conductive via that extends substantially through a substrate blank, such as a silicon wafer, at a street located adjacent to an outer periphery of the semiconductor device of the package. The outer connectors may include recesses that at least partially receive conductive columns protruding from a support substrate therefore. Assemblies may include the packages in stacked arrangement, without height-adding connectors.Type: ApplicationFiled: December 15, 2003Publication date: July 1, 2004Inventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Loo, Chua Swee Kwang
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Patent number: 6727116Abstract: A semiconductor device package is disclosed which is substantially die-sized with respect to each of the X, Y and Z axes. The package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the height of the peripheral edge. Each outer connector is formed by severing a conductive via that extends substantially through a substrate blank, such as a silicon wafer, at a street located adjacent to an outer periphery of the semiconductor device of the package. The outer connectors may include recesses that at least partially receive conductive columns protruding from a support substrate therefor. Assemblies may include the packages in stacked arrangement, without height-adding connectors.Type: GrantFiled: June 27, 2002Date of Patent: April 27, 2004Assignee: Micron Technology, Inc.Inventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Loo, Chua Swee Kwang
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Publication number: 20040026773Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.Type: ApplicationFiled: August 28, 2002Publication date: February 12, 2004Inventors: Eng Meow Koon, Low Siu Waf, Chan Min Yu, Chia Yong Poo, Ser Bok Leng, Zhou Wei