Patents by Inventor CHAN-SIC YOON

CHAN-SIC YOON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9627387
    Abstract: A semiconductor device includes a semiconductor substrate including active portions including first and second dopant regions, word lines on the substrate and extending in a first direction to intersect the active portions, first and second bit lines on the substrate and extending in a second direction to intersect the word lines, and contact structures in regions between the word lines and between the first and second bit lines when viewed from a plan view. The first and second bit lines are connected to the first dopant regions. The contact structures are in contact with the second dopant regions, respectively. The contact structures each include a contact plug and a contact pad. The contact pads contact the second dopant regions. A separation distance between the contact plugs and the first bit lines is less than separation distance between the contact pads and the first bit lines.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: April 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeonok Jung, Chan Ho Park, Chan-Sic Yoon, Kiseok Lee, Wonwoo Lee, Sunghee Han
  • Publication number: 20170025420
    Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.
    Type: Application
    Filed: February 4, 2016
    Publication date: January 26, 2017
    Inventors: Tae-Jin Park, Chan-sic Yoon, Ki-Seok Lee, Hyeon-Ok Jung, Dae-Ik Kim, Bong-Soo Kim, Yong-Kwan Kim, Eun-Jung Kim, Se-Myeong Jang, Min-su Choi, Sung-Hee Han, Yoo-Sang Hwang
  • Patent number: 9478548
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: October 25, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Yeong Lee, Chan-Sic Yoon, Ki-Seok Lee, Hyeon-Ok Jung
  • Publication number: 20160203992
    Abstract: A method of fabricating a semiconductor device includes forming a linear preliminary mask pattern in a first direction on a substrate. The preliminary mask pattern is patterned to provide a plurality of mask patterns that are aligned end-to-end with one another on the substrate and are separated by an exposed portion of the substrate between respective facing ends of the plurality of mask patterns. An auxiliary layer is formed to cover at least sidewalls of the facing ends to reduce a size of the exposed portion to provide a reduced exposed portion of the substrate and the reduced exposed portion of the substrate is etched to form a trench defining active patterns in the substrate aligned end-to-end with one another.
    Type: Application
    Filed: December 9, 2015
    Publication date: July 14, 2016
    Inventors: CHAN-SIC YOON, JIUNG PAK, KISEOK LEE, CHAN HO PARK, HYEONOK JUNG
  • Publication number: 20160197084
    Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.
    Type: Application
    Filed: December 29, 2015
    Publication date: July 7, 2016
    Inventors: Chan-Sic YOON, Ho-In RYU, Ki-Seok LEE, Chang-Hyun CHO
  • Publication number: 20160163637
    Abstract: A semiconductor device includes a semiconductor substrate including active portions including first and second dopant regions, word lines on the substrate and extending in a first direction to intersect the active portions, first and second bit lines on the substrate and extending in a second direction to intersect the word lines, and contact structures in regions between the word lines and between the first and second bit lines when viewed from a plan view. The first and second bit lines are connected to the first dopant regions. The contact structures are in contact with the second dopant regions, respectively. The contact structures each include a contact plug and a contact pad. The contact pads contact the second dopant regions. A separation distance between the contact plugs and the first bit lines is less than separation distance between the contact pads and the first bit lines.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 9, 2016
    Inventors: Hyeonok JUNG, Chan Ho PARK, Chan Sic YOON, Kiseok LEE, Wonwoo LEE, Sunghee HAN
  • Publication number: 20160035731
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening.
    Type: Application
    Filed: March 5, 2015
    Publication date: February 4, 2016
    Inventors: DO-YEONG LEE, CHAN-SIC YOON, KI-SEOK LEE, HYEON-OK JUNG