Abstract: A printed circuit board includes: a substrate body part including a first region and a second region, and including a first side and a second side; first upper redistribution patterns disposed on the first side in the first region; third upper redistribution patterns disposed on the first side in the second region; second upper redistribution patterns disposed on the first side and between the first and third upper redistribution patterns; connection patterns connecting the first upper redistribution patterns to the second upper redistribution patterns; a solder resist film including first recesses, second recesses, and third recesses, which respectively expose upper surfaces of the first, second and third upper redistribution patterns; and dummy wire patterns disposed within the second and third recesses and connecting the second upper redistribution patterns to the third upper redistribution patterns, wherein the first, second and third upper redistribution patterns are electrically connected to one another

Abstract: A crack detection chip includes a chip which includes an internal region and an external region surrounding the internal region, a guard ring formed inside the chip along an edge of the chip to define the internal region and the external region, an edge wiring disposed along an edge of the internal region in the form of a closed curve and a pad which is exposed on a surface of the chip and is connected to the edge wiring. The edge wiring is connected to a Time Domain Reflectometry (TDR) module which applies an incident wave to the edge wiring through the pad, and detects a reflected wave formed in the edge wiring to detect a position of a crack.

Abstract: A crack detection chip includes a chip which includes an internal region and an external region surrounding the internal region, a guard ring formed inside the chip along an edge of the chip to define the internal region and the external region, an edge wiring disposed along an edge of the internal region in the form of a closed curve and a pad which is exposed on a surface of the chip and is connected to the edge wiring. The edge wiring is connected to a Time Domain Reflectometry (TDR) module which applies an incident wave to the edge wiring through the pad, and detects a reflected wave formed in the edge wiring to detect a position of a crack.

Abstract: A crack detection chip includes a chip which includes an internal region and an external region surrounding the internal region, a guard ring formed inside the chip along an edge of the chip to define the internal region and the external region, an edge wiring disposed along an edge of the internal region in the form of a closed curve and a pad which is exposed on a surface of the chip and is connected to the edge wiring. The edge wiring is connected to a Time Domain Reflectometry (TDR) module which applies an incident wave to the edge wiring through the pad, and detects a reflected wave formed in the edge wiring to detect a position of a crack.

Abstract: A crack detection chip includes a chip which includes an internal region and an external region surrounding the internal region, a guard ring formed inside the chip along an edge of the chip to define the internal region and the external region, an edge wiring disposed along an edge of the internal region in the form of a closed curve and a pad which is exposed on a surface of the chip and is connected to the edge wiring. The edge wiring is connected to a Time Domain Reflectometry (TDR) module which applies an incident wave to the edge wiring through the pad, and detects a reflected wave formed in the edge wiring to detect a position of a crack.

Abstract: A test apparatus for a semiconductor package comprising an X-ray analyzer acquiring an X-ray image of the semiconductor package and detecting a thickness of the semiconductor package from the X-ray image, and a thermal reaction analyzer applying a voltage to the semiconductor package and detecting a failure position of the semiconductor package using a surface temperature of the semiconductor package and the thickness of the semiconductor package may be provided.

Abstract: A test apparatus for a semiconductor package comprising an X-ray analyzer acquiring an X-ray image of the semiconductor package and detecting a thickness of the semiconductor package from the X-ray image, and a thermal reaction analyzer applying a voltage to the semiconductor package and detecting a failure position of the semiconductor package using a surface temperature of the semiconductor package and the thickness of the semiconductor package may be provided.