Abstract: A method for forming an Electrostatic Discharge (ESD) protection circuit on a semiconductor device eliminates the formation of an ion-implanted well in the ESD protection circuit to lowering the impurity concentration of the well, thereby reducing the substrate resistance. Accordingly, the leakage current is reduced and snapback voltage characteristics are improved. The method includes forming a channel stop impurity layer over an entire peripheral circuit region of a substrate, including the ESD protection circuit region. A second, deeper, impurity layer is formed in a portion of the peripheral circuit region excluding the ESD protection circuit region, thereby forming one or more wells. A third impurity layer formed from impurities of a different type from the first impurity layer can be implanted in the portion of the peripheral circuit region so as to invert the polarity of a portion of the channel stop layer, thereby providing an active region for a complimentary transistor.

Abstract: A method for forming an Electrostatic Discharge (ESD) protection circuit on a semiconductor device eliminates the formation of an ion-implanted well in the ESD protection circuit to lowering the impurity concentration of the well, thereby reducing the substrate resistance. Accordingly, the leakage current is reduced and snapback voltage characteristics are improved. The method includes forming a channel stop impurity layer over an entire peripheral circuit region of a substrate, including the ESD protection circuit region. A second, deeper, impurity layer is formed in a portion of the peripheral circuit region excluding the ESD protection circuit region, thereby forming one or more wells. A third impurity layer formed from impurities of a different type from the first impurity layer can be implanted in the portion of the peripheral circuit region so as to invert the polarity of a portio of the channel stop layer, thereby providing an active region for a complimentary transistor.