Patents by Inventor Chan-sub Jun

Chan-sub Jun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device and test method thereof
    Patent number: 8243540
    Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: August 14, 2012
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Hyong-yong Lee, Chan-sub Jun
  • Semiconductor memory device and test method thereof
    Publication number: 20120014189
    Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.
    Type: Application
    Filed: September 12, 2011
    Publication date: January 19, 2012
    Inventors: Hyong-yong Lee, Chan-sub Jun
  • Semiconductor memory device and test method thereof
    Patent number: 8036052
    Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: October 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyong-yong Lee, Chan-sub Jun
  • Semiconductor memory device and test method thereof
    Publication number: 20080205174
    Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.
    Type: Application
    Filed: February 22, 2008
    Publication date: August 28, 2008
    Inventors: Hyong-yong Lee, Chan-sub Jun