Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.

Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.

Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.

Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.

Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.

Abstract: A semiconductor device includes first semiconductor patterns with protrusions formed on the sidewalls thereof, and second semiconductor patterns respectively coupled to the first semiconductor patterns and increasing in width away from joining surfaces where the first semiconductor patterns and the second semiconductor patterns are coupled.

Abstract: The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured to pass through the stacked structure; and contact plugs electrically coupled to the conductive layers, respectively, wherein each of the conductive layers includes a first region which has a first thickness, and a second region electrically coupled to the first region and a second thickness greater than the first thickness, and a second region of a lower conductive layer located under a second region of an upper conductive layer.

Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.

Abstract: The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured to pass through the stacked structure; and contact plugs electrically coupled to the conductive layers, respectively, wherein each of the conductive layers includes a first region which has a first thickness, and a second region electrically coupled to the first region and a second thickness greater than the first thickness, and a second region of a lower conductive layer located under a second region of an upper conductive layer.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes conductive patterns and interlayer insulating patterns having a stair structure and being alternately stacked, pad patterns connected to end portions of upper surfaces of the conductive patterns exposed through the stair structure, and a channel film penetrating the conductive patterns and the interlayer insulating patterns.

Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.

Abstract: The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured to pass through the stacked structure; and contact plugs electrically coupled to the conductive layers, respectively, wherein each of the conductive layers includes a first region which has a first thickness, and a second region electrically coupled to the first region and a second thickness greater than the first thickness, and a second region of a lower conductive layer located under a second region of an upper conductive layer.

Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.

Abstract: The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured to pass through the stacked structure; and contact plugs electrically coupled to the conductive layers, respectively, wherein each of the conductive layers includes a first region which has a first thickness, and a second region electrically coupled to the first region and a second thickness greater than the first thickness, and a second region of a lower conductive layer located under a second region of an upper conductive layer.

Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.

Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes conductive patterns and interlayer insulating patterns having a stair structure and being alternately stacked, pad patterns connected to end portions of upper surfaces of the conductive patterns exposed through the stair structure, and a channel film penetrating the conductive patterns and the interlayer insulating patterns.

Abstract: A semiconductor device includes first semiconductor patterns with protrusions formed on the sidewalls thereof, and second semiconductor patterns respectively coupled to the first semiconductor patterns and increasing in width away from joining surfaces where the first semiconductor patterns and the second semiconductor patterns are coupled.

Abstract: A semiconductor device includes a first interlayer dielectric layer formed over a semiconductor substrate, contact holes formed to penetrate the first interlayer dielectric layer, contact plugs formed within the contact holes, respectively, and spacers formed to partially cover upper sidewalk of the contact plugs within the contact holes.

Abstract: In a method of forming a contact plug of a semiconductor device, a nitride layer is prevented from being broken by forming a passivation layer over the nitride layer when contact holes are formed by etching an insulating layer between select lines formed over a semiconductor substrate. In an etch process of forming the contact plug, the passivation layer formed on sidewalls of the select lines is formed twice to protect the sidewalls of the select lines. Accordingly, the sidewalls of the select lines can be prevented from being damaged. Consequently, a process margin necessary to form a contact plug can be increased and, therefore, a smaller contact plug can be formed.