Abstract: The present invention relates to a novel naphthyridinone derivative compound, a pharmaceutically acceptable salt thereof, a hydrate thereof, or a stereoisomer thereof, which are each relevant to a compound for inhibiting ENPP1, a composition for inhibiting ENPP1, and a method for inhibiting ENPP1.

Abstract: The present invention relates to a novel benzotriazole derivative compound, a tautomer thereof, a pharmaceutically acceptable salt thereof, a hydrate thereof, or a stereoisomer thereof, which are related to a compound for inhibiting ENPP1, a composition for inhibiting ENPP1, and a method for inhibiting ENPP1.

Abstract: The present invention relates to a compound capable of lowering the flammability of a non-aqueous electrolyte when included in the non-aqueous electrolyte and improving the life properties of a battery by forming an electrode-electrolyte interface which is stable at high temperatures and low in resistance, and relates to a compound represented by Formula I descried herein, a non-aqueous electrolyte solution and a lithium secondary battery both including the compound, n, m, Ak, and X are described herein.

Abstract: A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.

Abstract: A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.

Abstract: A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.

Abstract: A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.

Abstract: A substrate for a semiconductor package having a reinforcing member that prevents or minimizes distortions is presented. The substrate for the semiconductor package includes a substrate body, an insulation layer, and a reinforcing member. The substrate body has a first region having a plurality of chip mount regions, a second region disposed along a periphery of the first region, a circuit pattern disposed in each chip mount region and a dummy pattern disposed along the second region. The insulation layer covers the first and second regions and has an opening exposing some portion of each circuit pattern. The reinforcing member is disposed in the second region and prevents deflection of the substrate body.

Abstract: A substrate for a semiconductor package having a reinforcing member that prevents or minimizes distortions is presented. The substrate for the semiconductor package includes a substrate body, an insulation layer, and a reinforcing member. The substrate body has a first region having a plurality of chip mount regions, a second region disposed along a periphery of the first region, a circuit pattern disposed in each chip mount region and a dummy pattern disposed along the second region. The insulation layer covers the first and second regions and has an opening exposing some portion of each circuit pattern. The reinforcing member is disposed in the second region and prevents deflection of the substrate body.

Abstract: A package stack includes at least two packages stacked on each other. Each package has a substrate, a circuit pattern positioned on the substrate, a semiconductor chip attached to the substrate, and a number of through-vias formed on a lateral surface. A number of electrical connection members are attached to the through-vias so as to electrically connect the packages to each other. The through-vias are vertically positioned on the lateral or side surface of the packages. And a solder ball is attached to the lower surface of the substrate of the lowest package.