Abstract: Some embodiments of the present disclosure relate to a contact formed to a source or drain region of a “finned” field-effect transistor (FinFET). An epitaxial material is formed over the source or drain region, which includes a diamond-shaped cross-section with top and bottom surfaces. A capping layer is formed over the top and bottom surfaces. The source or drain region is subjected to a first etch to remove the capping layer surrounding the top surfaces of the diamond-shaped cross-section. A protective layer is formed within the top surfaces. A second etch of the capping layer is performed to remove the capping layer surrounding the bottom surfaces of the diamond-shaped cross-section, while using the protective layer to prevent etching of the top surfaces by the second etch. A contact is formed to the source or drain region, which surrounds the source or drain region on the top and bottom surfaces.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including pattering a mandrel layer disposed over a semiconductor device layer to form a mandrel, forming a first set of spacers on sidewalls of the mandrel using a first material, selectively removing the mandrel disposed between the first set of spacers. The method further includes after removing the mandrel, using the first set of spacers as a first set of mandrels, forming a second set of spacers on sidewalls of the first set of mandrels using a second material, the second material having a different etch selectivity from the etch selectivity of the first material, the second set of spacers have substantially flat top surfaces, and selectively removing the first set of mandrels disposed between the second set of spacers.

Abstract: Some embodiments of the present disclosure relate to a contact formed to a source or drain region of a “finned” field-effect transistor (FinFET). An epitaxial material is formed over the source or drain region, which includes a diamond-shaped cross-section with top and bottom surfaces. A capping layer is formed over the top and bottom surfaces. The source or drain region is subjected to a first etch to remove the capping layer surrounding the top surfaces of the diamond-shaped cross-section. A protective layer is formed within the top surfaces. A second etch of the capping layer is performed to remove the capping layer surrounding the bottom surfaces of the diamond-shaped cross-section, while using the protective layer to prevent etching of the top surfaces by the second etch. A contact is formed to the source or drain region, which surrounds the source or drain region on the top and bottom surfaces.

Abstract: Some embodiments of the present disclosure relate to a contact formed to a source or drain region of a “finned” field-effect transistor (FinFET). An epitaxial material is formed over the source or drain region, which includes a diamond-shaped cross-section with top and bottom surfaces. A capping layer is formed over the top and bottom surfaces. The source or drain region is subjected to a first etch to remove the capping layer surrounding the top surfaces of the diamond-shaped cross-section. A protective layer is formed within the top surfaces. A second etch of the capping layer is performed to remove the capping layer surrounding the bottom surfaces of the diamond-shaped cross-section, while using the protective layer to prevent etching of the top surfaces by the second etch. A contact is formed to the source or drain region, which surrounds the source or drain region on the top and bottom surfaces.

Abstract: A method of fabricating an interconnect line comprises forming a wall, depositing an etch mask having a thickness that decreases towards a bottom of the wall, and isotropically etching the wall at the bottom to form the interconnect line having a pre-determined gap between the substrate and a bottom of the line.

Abstract: Disclosed herein is a method of etching a trench in silicon overlying a dielectric material which reduces or substantially eliminates notching at the base of the trench, while reducing scalloping on the sidewalls of the trench. The method comprises etching a first portion of a trench by exposing a silicon substrate, through a patterned masking layer, to a plasma generated from a fluorine-containing gas. This etching is followed by a polymer deposition step comprising exposing the substrate to a plasma generated from a gas which is capable of forming a polymer on etched silicon surfaces. The etching and polymer deposition steps are repeated for a number of cycles, depending on the desired depth of the first portion of the trench. The final portion of the trench is etched by exposing the silicon to a plasma generated from a combination of a fluorine-containing gas and a polymer-forming gas.

Abstract: Disclosed herein is a method of etching a trench in silicon overlying a dielectric material which reduces or substantially eliminates notching at the base of the trench, while reducing scalloping on the sidewalls of the trench. The method comprises etching a first portion of a trench by exposing a silicon substrate, through a patterned masking layer, to a plasma generated from a fluorine-containing gas. This etching is followed by a polymer deposition step comprising exposing the substrate to a plasma generated from a gas which is capable of forming a polymer on etched silicon surfaces. The etching and polymer deposition steps are repeated for a number of cycles, depending on the desired depth of the first portion of the trench. The final portion of the trench is etched by exposing the silicon to a plasma generated from a combination of a fluorine-containing gas and a polymer-forming gas.

Abstract: A method of forming a notch silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate layer is etched to a first desired depth using a plasma generated from a first source gas. During the etch, etch byproducts deposit on upper sidewalls of the silicon-containing gate layer which are exposed during etching, forming a first passivation layer which protects the upper silicon-containing gate layer sidewalls from etching during subsequent processing steps. A relatively high substrate bias power is used during this first etch step to ensure that the passivation layer adheres properly to the upper silicon-containing gate sidewalls.

Abstract: A method of forming a notched silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate layer is etched to a first desired depth using a plasma generated from a first source gas. During the etch, etch byproducts deposit on upper sidewalls of the silicon-containing gate layer which are exposed during etching, forming a first passivation layer which protects the upper silicon-containing gate layer sidewalls from etching during subsequent processing steps. A relatively high substrate bias power is used during this first etch step to ensure that the passivation layer adheres properly to the upper silicon-containing gate sidewalls.

Abstract: Methods and compositions for treating a wafer's layer stack following metal etching are provided. The methods involve providing a semiconductor wafer layer stack in a plasma processing system following metal etch, and treating the layer stack with one or more process gases in a plasma processing system, where at least one of the process gases contains helium and water and/or oxygen, or comparable gases. The methods and compositions reduce corrosion and polymer fence for a wafer's layer stack relative to conventional passivation and strip processes without helium, decrease the time necessary for passivation, increase the strip rate, and/or improve strip uniformity.