Abstract: A method of partitioning a memory resource, associated with a multi-threaded processor, includes defining the memory resource to include first and second portions that are dedicated to the first and second threads respectively. A third portion of the memory resource is then designated as being shared between the first and second threads. Upon receipt of an information item, (e.g., a microinstruction associated with the first thread and to be stored in the memory resource), a history of Least Recently Used (LRU) portions is examined to identify a location in either the first or the third portion, but not the second portion, as being a least recently used portion. The second portion is excluded from this examination on account of being dedicated to the second thread. The information item is then stored within a location, within either the first or the third portion, identified as having been least recently used.

Abstract: A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.

Abstract: A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.

Abstract: A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.

Abstract: A circuit and method for supplying output length marks indicative of the first bytes and last bytes of instructions in a block of instruction code to an instruction decoder. A block of instruction code is input to an input buffer. A plurality of programmable logic arrays (PLAs) is coupled to receive predetermined sets of bytes from the input buffer and to provide instruction information at an output. The output of the PLAs is coupled to fast carry chain circuitry, which serially processes the information from the PLAs and provides a START mark upon each finding of a first byte of an instruction and an END mark upon each finding of a last byte of an instruction. Length information is provided to wraparound logic for length calculations spanning into the next input buffer of instruction code. A FCC latch latches the output length marks from the fast carry chain circuitry and provides an output to the instruction decoder.

Abstract: A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.