Patents by Inventor Chan Won KIM

Chan Won KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9793133
    Abstract: Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding layer. A second molding layer can be formed on the first molding layer so that the first hole is retained in the first molding layer and a second hole can be formed through the second molding layer to connect with the first hole. A capacitor electrode can be formed in the first and second holes.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: October 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-Won Kim, Jung-Woo Seo, Kee-Hong Lee, Kyoung-Ryul Yoon, Seong-Kyu Yun
  • Patent number: 9431476
    Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
  • Publication number: 20160225845
    Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.
    Type: Application
    Filed: March 31, 2016
    Publication date: August 4, 2016
    Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
  • Publication number: 20160150355
    Abstract: A method of controlling an operation mode of an electronic device and the electronic device therefore are provided. The method includes verifying an operation mode of the first electronic device when it is verified that a second electronic device is approached within a predetermined range while transmitting and receiving data with a third electronic device and changing a first mode to a second mode when the first electronic device operates in the first mode.
    Type: Application
    Filed: July 11, 2014
    Publication date: May 26, 2016
    Inventors: Sung-Sik YOO, Byung-soo KIM, Seul-A KIM, Chan-Won KIM, Seung-Yeon EOM, Doo-Man LEE, Han-Vit CHUNG, Seung-Jin CHOI
  • Patent number: 9330960
    Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: May 3, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
  • Patent number: 9324609
    Abstract: Methods of forming a hard mask capable of implementing an electrode having a high aspect ratio are provided. A molding layer may be formed on a substrate. A sacrificial layer may be formed on the molding layer. First mask patterns may be formed in parallel in the sacrificial layer. After the first mask patterns are formed, second mask patterns, which cross the first mask patterns and are in parallel, may be formed in the sacrificial layer. The first mask patterns and the second mask patterns may have materials more opaque than the sacrificial layer. Upper surfaces of the sacrificial layer, the first mask patterns and the second mask patterns may be exposed at the same horizontal level. The sacrificial layer may be removed. Openings, which pass through the molding layer, may be formed using the first mask patterns and the second mask patterns as etch masks. Electrodes may be formed in the openings.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-Won Kim, Jung-Woo Seo
  • Publication number: 20150364366
    Abstract: Methods of forming a hard mask capable of implementing an electrode having a high aspect ratio are provided. A molding layer may be formed on a substrate. A sacrificial layer may be formed on the molding layer. First mask patterns may be formed in parallel in the sacrificial layer. After the first mask patterns are formed, second mask patterns, which cross the first mask patterns and are in parallel, may be formed in the sacrificial layer. The first mask patterns and the second mask patterns may have materials more opaque than the sacrificial layer. Upper surfaces of the sacrificial layer, the first mask patterns and the second mask patterns may be exposed at the same horizontal level. The sacrificial layer may be removed. Openings, which pass through the molding layer, may be formed using the first mask patterns and the second mask patterns as etch masks. Electrodes may be formed in the openings.
    Type: Application
    Filed: March 30, 2015
    Publication date: December 17, 2015
    Inventors: Chan-Won KIM, Jung-Woo Seo
  • Patent number: 9123657
    Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an interlayer insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayer insulating layer, forming trenches in the first mask layer exposing the interlayer insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayer insulating layer may be greater than that of the key mask patterns with respect to the interlayer insulating layer.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: September 1, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minjoon Park, Junho Yoon, Je-Woo Han, Chan-Won Kim
  • Publication number: 20150214289
    Abstract: Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding layer. A second molding layer can be formed on the first molding layer so that the first hole is retained in the first molding layer and a second hole can be formed through the second molding layer to connect with the first hole. A capacitor electrode can be formed in the first and second holes.
    Type: Application
    Filed: October 8, 2014
    Publication date: July 30, 2015
    Inventors: Chan-Won Kim, Jung-Woo Seo, Kee-Hong Lee, Kyoung-Ryul Yoon, Seong-Kyu Yun
  • Publication number: 20150079791
    Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an interlayered insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayered insulating layer, forming trenches in the first mask layer exposing the interlayered insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayered insulating layer may be greater than that of the key mask patterns with respect to the interlayered insulating layer.
    Type: Application
    Filed: July 9, 2014
    Publication date: March 19, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Minjoon PARK, Junho YOON, Je-Woo HAN, Chan-Won KIM
  • Patent number: 8932003
    Abstract: Disclosed is a vacuum self-priming pump in which a main pumping chamber and a sub-pumping chamber divided from each other by a diaphragm are provided within a case, main impellers and a sub-impeller rotated by a motor are respectively installed within the main pump chamber and the sub-pumping chamber such that a space is formed between a pair of left and right main impellers, and connection pipes are respectively formed between suction pipes of the main pumping chamber and the sub-pumping chamber and between discharge pipes of the main pumping chamber and the sub-pumping chamber, so as to more rapidly suck fluid every pumping operation and to effectively pump the fluid without clogging even if the pumped fluid contains various sludge or solid matter.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: January 13, 2015
    Inventor: Chan Won Kim
  • Publication number: 20140361403
    Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 11, 2014
    Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
  • Publication number: 20120315126
    Abstract: Disclosed is a vacuum self-priming pump in which a main pumping chamber and a sub-pumping chamber divided from each other by a diaphragm are provided within a case, main impellers and a sub-impeller rotated by a motor are respectively installed within the main pump chamber and the sub-pumping chamber such that a space is formed between a pair of left and right main impellers, and connection pipes are respectively formed between suction pipes of the main pumping chamber and the sub-pumping chamber and between discharge pipes of the main pumping chamber and the sub-pumping chamber, so as to more rapidly suck fluid every pumping operation and to effectively pump the fluid without clogging even if the pumped fluid contains various sludge or solid matter.
    Type: Application
    Filed: May 16, 2012
    Publication date: December 13, 2012
    Inventor: Chan Won KIM