Patents by Inventor Chan Won KIM

Chan Won KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154131
    Abstract: Provided is a catalyst layer for fuel cell having improved heat-dissipating performance and durability. The catalyst layer for fuel cell according to the present invention is a catalyst layer for fuel cell comprising a first composite and a second composite, wherein the first composite includes: a supporting material, a catalyst including metal particles supported on the supporting material, and a first ionomer coated on the surface of the catalyst; the second composite includes a heat-dissipating material and a second ionomer, the second ionomer is not coated on the surface of the catalyst, and the first ionomer and the second ionomer are identical with or different from each other.
    Type: Application
    Filed: February 15, 2022
    Publication date: May 9, 2024
    Inventors: Jung Ho KIM, Jun Young KIM, Kah Young SONG, Nak Won KONG, Ju Sung LEE, Kyoung Sik NAM, Chan Mi PARK
  • Publication number: 20240146103
    Abstract: Embodiments of the inventive concept provide a wireless power apparatus for a substrate treating apparatus and a manufacturing method for the wireless power apparatus for the substrate treating apparatus for preventing a heat generation by preventing a generation of an eddy current in a coupling element, if the coupling element is used around an outer housing at which an induced magnetic field is formed. The inventive concept provides a wireless power apparatus for a substrate treating apparatus.
    Type: Application
    Filed: April 26, 2023
    Publication date: May 2, 2024
    Applicant: SEMES CO., LTD.
    Inventors: Chan Young Choi, Ki Won Han, Wan Hee Jeong, Kyo Bong Kim, Hee Chan Kim, Doo Hyun Baek, Sang-Oh Kim, Hee Jae Byun
  • Publication number: 20240130892
    Abstract: Glaucoma is a type of eye disease caused by high intraocular pressure (IOP). An increase in IOP causes damage to the appearance and function of the optic nerve and, when left untreated, leads to vision loss. However, once inserted, the conventional aqueous humor drainage devices implanted to control IOP continuously discharge a certain amount of aqueous humor regardless of how high or low the IOP is and thus have difficulty in effectively controlling the IOP. The present disclosure, which has been devised to address the above problems, relates to a novel aqueous humor drainage device for controlling IOP. The aqueous humor drainage device of the present disclosure, which is a double-layer aqueous humor drainage device having a tube made of a shape memory polymer included therein, can control both low IOP and high IOP and thus has an excellent effect of maintaining IOP within a clinically acceptable range.
    Type: Application
    Filed: June 8, 2021
    Publication date: April 25, 2024
    Inventors: Chan Yun KIM, Hyoung Won BAE, Wungrak CHOI
  • Publication number: 20240132021
    Abstract: An apparatus for controlling a discharge pressure of a fluid includes: a pump configured to suck the fluid through an inlet or to discharge the sucked fluid through an outlet; a distributor connected to the pump and to an injection nozzle provided by a sensor and configured to distribute the fluid discharged from the pump to the sensor; and a controller. The controller is configured to control the pump to operate selectively in accordance with detection of contamination of the sensor and to control operation of the distributor to be forcibly delayed during operation of the pump such that the fluid distributed to the sensor, when detected as being contaminated, is controlled to reach a selected required discharge pressure of different required discharge pressures selected in accordance with water amount information and a degree of contamination of the sensor.
    Type: Application
    Filed: April 30, 2023
    Publication date: April 25, 2024
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, DY AUTO CORPORATION
    Inventors: Young Joon Shin, Chan Mook Choi, Gyu Won Han, Jong Min Park, Jin Hee Lee, Jong Wook Lee, Min Wook Park, Seong Jun Kim, Hyeong Jun Kim, Sun Ju Kim
  • Publication number: 20240125908
    Abstract: A method for manufacturing a LiDAR device is proposed. The method may include providing a LiDAR module including a laser emitting module and a laser detecting module to a target region. The method may also include adjusting, on the basis of first detecting data obtained from the laser detecting module, a relative position of a detecting optic module with respect to the laser detecting module. The method may further include adjusting, on the basis of image data obtained from at least one image sensor, a relative position of an emitting optic module with respect to the laser emitting module.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 18, 2024
    Inventors: Chan M LIM, Dong Kyu KIM, Chang Mo JEONG, Hoon Il JEONG, Eunsung KWON, Junhyun JO, Bumsik WON, Suwoo NOH, Sang Shin BAE, Seong Min YUN, Jong Hyun YIM
  • Publication number: 20240119851
    Abstract: The present invention relates to a method and system for providing language learning services. The method of providing language learning services, according to the present invention, the method may include: activating, in response to receiving an input for acquiring a learning target image through a user terminal, a camera of the user terminal; specifying at least a portion of an image taken by the camera as the learning target image; receiving language learning information for the learning target image from a server; providing the language learning information to the user terminal; and storing, based on a request for storing of the language learning information, the language learning information in association with the learning target image, such that the learning target image is used in conjunction with learning of the language learning information.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 11, 2024
    Inventors: Eun Young LEE, Min Jung KIM, Yeun Hee KANG, Bong Hyun CHOI, Tae Un KIM, Soo Hyun LEE, Young Ho KIM, Chan Kyu CHOI, Jin Mo KU, Jong Won KIM
  • Publication number: 20240088347
    Abstract: A prelithiated negative electrode, and a secondary battery including a prelithiated electrode, including a negative electrode current collector; and a negative electrode active material layer present on at least one surface of the negative electrode current collector. The negative electrode active material layer includes high-capacity artificial graphite having no carbon coating. The negative electrode active material layer is prelithiated, and the content of lithium intercalated to the prelithiated negative electrode active material layer is 3% to 5% based on the lithium content intercalated when the negative electrode is charged to 100%.
    Type: Application
    Filed: November 11, 2020
    Publication date: March 14, 2024
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Hee-Won CHOI, Ye-Ri KIM, Chan-Ki PARK, Mi-Ru JO, Oh-Byong CHAE, Seung-Hae HWANG
  • Patent number: 11923035
    Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan Ho Lee, Tae Min Choi, Jeong Kyun Kim, Hyeong Cheol Kim, Suk Youn, Ju Chang Lee, Kyu Won Choi
  • Patent number: 9793133
    Abstract: Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding layer. A second molding layer can be formed on the first molding layer so that the first hole is retained in the first molding layer and a second hole can be formed through the second molding layer to connect with the first hole. A capacitor electrode can be formed in the first and second holes.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: October 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-Won Kim, Jung-Woo Seo, Kee-Hong Lee, Kyoung-Ryul Yoon, Seong-Kyu Yun
  • Patent number: 9431476
    Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
  • Publication number: 20160225845
    Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.
    Type: Application
    Filed: March 31, 2016
    Publication date: August 4, 2016
    Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
  • Publication number: 20160150355
    Abstract: A method of controlling an operation mode of an electronic device and the electronic device therefore are provided. The method includes verifying an operation mode of the first electronic device when it is verified that a second electronic device is approached within a predetermined range while transmitting and receiving data with a third electronic device and changing a first mode to a second mode when the first electronic device operates in the first mode.
    Type: Application
    Filed: July 11, 2014
    Publication date: May 26, 2016
    Inventors: Sung-Sik YOO, Byung-soo KIM, Seul-A KIM, Chan-Won KIM, Seung-Yeon EOM, Doo-Man LEE, Han-Vit CHUNG, Seung-Jin CHOI
  • Patent number: 9330960
    Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: May 3, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
  • Patent number: 9324609
    Abstract: Methods of forming a hard mask capable of implementing an electrode having a high aspect ratio are provided. A molding layer may be formed on a substrate. A sacrificial layer may be formed on the molding layer. First mask patterns may be formed in parallel in the sacrificial layer. After the first mask patterns are formed, second mask patterns, which cross the first mask patterns and are in parallel, may be formed in the sacrificial layer. The first mask patterns and the second mask patterns may have materials more opaque than the sacrificial layer. Upper surfaces of the sacrificial layer, the first mask patterns and the second mask patterns may be exposed at the same horizontal level. The sacrificial layer may be removed. Openings, which pass through the molding layer, may be formed using the first mask patterns and the second mask patterns as etch masks. Electrodes may be formed in the openings.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan-Won Kim, Jung-Woo Seo
  • Publication number: 20150364366
    Abstract: Methods of forming a hard mask capable of implementing an electrode having a high aspect ratio are provided. A molding layer may be formed on a substrate. A sacrificial layer may be formed on the molding layer. First mask patterns may be formed in parallel in the sacrificial layer. After the first mask patterns are formed, second mask patterns, which cross the first mask patterns and are in parallel, may be formed in the sacrificial layer. The first mask patterns and the second mask patterns may have materials more opaque than the sacrificial layer. Upper surfaces of the sacrificial layer, the first mask patterns and the second mask patterns may be exposed at the same horizontal level. The sacrificial layer may be removed. Openings, which pass through the molding layer, may be formed using the first mask patterns and the second mask patterns as etch masks. Electrodes may be formed in the openings.
    Type: Application
    Filed: March 30, 2015
    Publication date: December 17, 2015
    Inventors: Chan-Won KIM, Jung-Woo Seo
  • Patent number: 9123657
    Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an interlayer insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayer insulating layer, forming trenches in the first mask layer exposing the interlayer insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayer insulating layer may be greater than that of the key mask patterns with respect to the interlayer insulating layer.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: September 1, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minjoon Park, Junho Yoon, Je-Woo Han, Chan-Won Kim
  • Publication number: 20150214289
    Abstract: Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding layer. A second molding layer can be formed on the first molding layer so that the first hole is retained in the first molding layer and a second hole can be formed through the second molding layer to connect with the first hole. A capacitor electrode can be formed in the first and second holes.
    Type: Application
    Filed: October 8, 2014
    Publication date: July 30, 2015
    Inventors: Chan-Won Kim, Jung-Woo Seo, Kee-Hong Lee, Kyoung-Ryul Yoon, Seong-Kyu Yun
  • Publication number: 20150079791
    Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an interlayered insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayered insulating layer, forming trenches in the first mask layer exposing the interlayered insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayered insulating layer may be greater than that of the key mask patterns with respect to the interlayered insulating layer.
    Type: Application
    Filed: July 9, 2014
    Publication date: March 19, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Minjoon PARK, Junho YOON, Je-Woo HAN, Chan-Won KIM
  • Patent number: 8932003
    Abstract: Disclosed is a vacuum self-priming pump in which a main pumping chamber and a sub-pumping chamber divided from each other by a diaphragm are provided within a case, main impellers and a sub-impeller rotated by a motor are respectively installed within the main pump chamber and the sub-pumping chamber such that a space is formed between a pair of left and right main impellers, and connection pipes are respectively formed between suction pipes of the main pumping chamber and the sub-pumping chamber and between discharge pipes of the main pumping chamber and the sub-pumping chamber, so as to more rapidly suck fluid every pumping operation and to effectively pump the fluid without clogging even if the pumped fluid contains various sludge or solid matter.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: January 13, 2015
    Inventor: Chan Won Kim
  • Publication number: 20140361403
    Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 11, 2014
    Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee