Patents by Inventor Chan Won KIM
Chan Won KIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9793133Abstract: Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding layer. A second molding layer can be formed on the first molding layer so that the first hole is retained in the first molding layer and a second hole can be formed through the second molding layer to connect with the first hole. A capacitor electrode can be formed in the first and second holes.Type: GrantFiled: October 8, 2014Date of Patent: October 17, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-Won Kim, Jung-Woo Seo, Kee-Hong Lee, Kyoung-Ryul Yoon, Seong-Kyu Yun
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Patent number: 9431476Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.Type: GrantFiled: March 31, 2016Date of Patent: August 30, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
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Publication number: 20160225845Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.Type: ApplicationFiled: March 31, 2016Publication date: August 4, 2016Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
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Publication number: 20160150355Abstract: A method of controlling an operation mode of an electronic device and the electronic device therefore are provided. The method includes verifying an operation mode of the first electronic device when it is verified that a second electronic device is approached within a predetermined range while transmitting and receiving data with a third electronic device and changing a first mode to a second mode when the first electronic device operates in the first mode.Type: ApplicationFiled: July 11, 2014Publication date: May 26, 2016Inventors: Sung-Sik YOO, Byung-soo KIM, Seul-A KIM, Chan-Won KIM, Seung-Yeon EOM, Doo-Man LEE, Han-Vit CHUNG, Seung-Jin CHOI
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Patent number: 9330960Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.Type: GrantFiled: June 5, 2014Date of Patent: May 3, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
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Patent number: 9324609Abstract: Methods of forming a hard mask capable of implementing an electrode having a high aspect ratio are provided. A molding layer may be formed on a substrate. A sacrificial layer may be formed on the molding layer. First mask patterns may be formed in parallel in the sacrificial layer. After the first mask patterns are formed, second mask patterns, which cross the first mask patterns and are in parallel, may be formed in the sacrificial layer. The first mask patterns and the second mask patterns may have materials more opaque than the sacrificial layer. Upper surfaces of the sacrificial layer, the first mask patterns and the second mask patterns may be exposed at the same horizontal level. The sacrificial layer may be removed. Openings, which pass through the molding layer, may be formed using the first mask patterns and the second mask patterns as etch masks. Electrodes may be formed in the openings.Type: GrantFiled: March 30, 2015Date of Patent: April 26, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-Won Kim, Jung-Woo Seo
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Publication number: 20150364366Abstract: Methods of forming a hard mask capable of implementing an electrode having a high aspect ratio are provided. A molding layer may be formed on a substrate. A sacrificial layer may be formed on the molding layer. First mask patterns may be formed in parallel in the sacrificial layer. After the first mask patterns are formed, second mask patterns, which cross the first mask patterns and are in parallel, may be formed in the sacrificial layer. The first mask patterns and the second mask patterns may have materials more opaque than the sacrificial layer. Upper surfaces of the sacrificial layer, the first mask patterns and the second mask patterns may be exposed at the same horizontal level. The sacrificial layer may be removed. Openings, which pass through the molding layer, may be formed using the first mask patterns and the second mask patterns as etch masks. Electrodes may be formed in the openings.Type: ApplicationFiled: March 30, 2015Publication date: December 17, 2015Inventors: Chan-Won KIM, Jung-Woo Seo
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Patent number: 9123657Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an interlayer insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayer insulating layer, forming trenches in the first mask layer exposing the interlayer insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayer insulating layer may be greater than that of the key mask patterns with respect to the interlayer insulating layer.Type: GrantFiled: July 9, 2014Date of Patent: September 1, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Minjoon Park, Junho Yoon, Je-Woo Han, Chan-Won Kim
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Publication number: 20150214289Abstract: Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding layer. A second molding layer can be formed on the first molding layer so that the first hole is retained in the first molding layer and a second hole can be formed through the second molding layer to connect with the first hole. A capacitor electrode can be formed in the first and second holes.Type: ApplicationFiled: October 8, 2014Publication date: July 30, 2015Inventors: Chan-Won Kim, Jung-Woo Seo, Kee-Hong Lee, Kyoung-Ryul Yoon, Seong-Kyu Yun
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Publication number: 20150079791Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an interlayered insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayered insulating layer, forming trenches in the first mask layer exposing the interlayered insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayered insulating layer may be greater than that of the key mask patterns with respect to the interlayered insulating layer.Type: ApplicationFiled: July 9, 2014Publication date: March 19, 2015Applicant: Samsung Electronics Co., Ltd.Inventors: Minjoon PARK, Junho YOON, Je-Woo HAN, Chan-Won KIM
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Patent number: 8932003Abstract: Disclosed is a vacuum self-priming pump in which a main pumping chamber and a sub-pumping chamber divided from each other by a diaphragm are provided within a case, main impellers and a sub-impeller rotated by a motor are respectively installed within the main pump chamber and the sub-pumping chamber such that a space is formed between a pair of left and right main impellers, and connection pipes are respectively formed between suction pipes of the main pumping chamber and the sub-pumping chamber and between discharge pipes of the main pumping chamber and the sub-pumping chamber, so as to more rapidly suck fluid every pumping operation and to effectively pump the fluid without clogging even if the pumped fluid contains various sludge or solid matter.Type: GrantFiled: May 16, 2012Date of Patent: January 13, 2015Inventor: Chan Won Kim
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Publication number: 20140361403Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.Type: ApplicationFiled: June 5, 2014Publication date: December 11, 2014Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
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Publication number: 20120315126Abstract: Disclosed is a vacuum self-priming pump in which a main pumping chamber and a sub-pumping chamber divided from each other by a diaphragm are provided within a case, main impellers and a sub-impeller rotated by a motor are respectively installed within the main pump chamber and the sub-pumping chamber such that a space is formed between a pair of left and right main impellers, and connection pipes are respectively formed between suction pipes of the main pumping chamber and the sub-pumping chamber and between discharge pipes of the main pumping chamber and the sub-pumping chamber, so as to more rapidly suck fluid every pumping operation and to effectively pump the fluid without clogging even if the pumped fluid contains various sludge or solid matter.Type: ApplicationFiled: May 16, 2012Publication date: December 13, 2012Inventor: Chan Won KIM