Abstract: A semiconductor chip testing system comprises a tester with a predetermined number of pin drivers; high current and low current drivers are connected between the pin drivers of the tester and a ground voltage applying terminal of the semiconductor chip to be tested. Control signals are applied to the pin drivers according to a testing method of a tester to generate ground noise at the ground voltage applying terminal of the semiconductor chip, thereby performing a ground noise immunity test on the semiconductor chip. A semiconductor chip tester comprises a predetermined number of pin drivers with large current driving capacity; and a predetermined number of pin drivers with small current driving capacity, wherein ground noise control signals are applied to the pin drivers with large current driving capacity according to a test program to apply ground noise to a ground voltage applying terminal of a semiconductor chip to be tested while the semiconductor chip is tested according to the test program.