Abstract: A semiconductor device is provided. The semiconductor device includes a first coil section that receives a first clock signal from a reader, a power generator that is electrically connected to the first coil section in accordance with a switching operation of a switch, a first near-field communication (NFC) chip that is electrically connected to the power generator and receives electric power in accordance with the first clock signal, a second NFC chip that generates a switching operation control signal for controlling the switching operation of the switch, and a second coil section that is electrically connected to the second NFC chip and receives a second clock signal from the reader.

Abstract: A semiconductor device is provided. The semiconductor device includes a first coil section that receives a first clock signal from a reader, a power generator that is electrically connected to the first coil section in accordance with a switching operation of a switch, a first near-field communication (NFC) chip that is electrically connected to the power generator and receives electric power in accordance with the first clock signal, a second NFC chip that generates a switching operation control signal for controlling the switching operation of the switch, and a second coil section that is electrically connected to the second NFC chip and receives a second clock signal from the reader.

Abstract: A mobile device and related power management method are disclosed. The power management method includes detecting a level of residual battery power, and selectively enabling the provision of power to the smart card and the RF chip in accordance with the detected level of residual battery power.

Abstract: A mobile device and related power management method are disclosed. The power management method includes detecting a level of residual battery power, and selectively enabling the provision of power to the smart card and the RF chip in accordance with the detected level of residual battery power.

Abstract: A mobile device and related power management method are disclosed. The power management method includes detecting a level of residual battery power, and selectively enabling the provision of power to the smart card and the RF chip in accordance with the detected level of residual battery power.

Abstract: A semiconductor integrated circuit is provided, which includes: a first circuit; a second circuit; a data BUS; and first and second encryption/decryption circuits for encrypting/decrypting data transmitted between the first and second circuits on the data bus. The first encryption/decryption circuit is for encrypting data output from the first circuit, outputting the encrypted data to the data BUS, decrypting an encrypted data received from the second encryption/decryption circuit, and providing the decrypted data to the first circuit. The second encryption/decryption circuit is for decrypting the encrypted data received from the first encryption/decryption circuit, providing the decrypted data to the second circuit, encrypting data output from the second circuit, and outputting the encrypted data to the data BUS.

Abstract: Example embodiments relate to an internal power supply voltage generating device. The internal power supply voltage generating device may include a start-up voltage generating part, a reference voltage generating part, and/or an internal power supply voltage generating part. The start-up voltage generating part may be configured to generate a start-up voltage using an external power supply voltage. The reference voltage generating part may be configured to generate a reference voltage using the start-up voltage. The internal power supply voltage generating part may be configured to generate an internal power supply voltage using the reference voltage and the external power supply voltage. The start-up voltage generating part may be turned off by the reference voltage generated by the reference voltage generating part. Example embodiments also relate to a method of generating an internal power supply voltage.

Abstract: A clock signal generator for a USB device. The clock signal generator includes a control circuit and a clock generator that does not need to include a crystal oscillator. The control circuit counts the cycle of the clock signal during the period between two sync signals successively inputted, and generates a frequency control signal corresponding to the count value. The clock generator generates the clock signal with a frequency corresponding to the frequency control signal. The clock signal generator can generate a clock signal that is suitable for the data transfer rate defined, in the USB specification. In addition, the clock; signal generator can generate an RX clock signal so that an RX data signal can be recovered with its energy being stable.

Abstract: Provided is a smart card for communicating with a host computer through a universal serial bus (USB). The smart card includes an internal clock signal generator to generate an internal clock signal, a period detector to detect a period of the internal clock signal and to generate a control code according to the detected period, and a transmission clock generator to generate a transmission clock signal which varies from the internal clock signal according to the control code. The smart card transfers data in sync with the transmission clock signal.

Abstract: A mobile device and related power management method are disclosed. The power management method includes detecting a level of residual battery power, and selectively enabling the provision of power to the smart card and the RF chip in accordance with the detected level of residual battery power.

Abstract: Example embodiments relate to an internal power supply voltage generating device. The internal power supply voltage generating device may include a start-up voltage generating part, a reference voltage generating part, and/or an internal power supply voltage generating part. The start-up voltage generating part may be configured to generate a start-up voltage using an external power supply voltage. The reference voltage generating part may be configured to generate a reference voltage using the start-up voltage. The internal power supply voltage generating part may be configured to generate an internal power supply voltage using the reference voltage and the external power supply voltage. The start-up voltage generating part may be turned off by the reference voltage generated by the reference voltage generating part. Example embodiments also relate to a method of generating an internal power supply voltage.

Abstract: A clock signal generator for a USB device. The clock signal generator includes a control circuit and a clock generator that does not need to include a crystal oscillator. The control circuit counts the cycle of the clock signal during the period between two sync signals successively inputted, and generates a frequency control signal corresponding to the count value. The clock generator generates the clock signal with a frequency corresponding to the frequency control signal. The clock signal generator can generate a clock signal that is suitable for the data transfer rate defined, in the USB specification. In addition, the clock; signal generator can generate an RX clock signal so that an RX data signal can be recovered with its energy being stable.

Abstract: An internal voltage converter and method is provided capable of reducing power consumption using a selective voltage reference, a semiconductor device including the internal voltage converter. A semiconductor device uses the internal voltage converter which discriminates an IVC stand-by state from a normal operation state, selects a voltage reference with low power consumption among selective voltage references in the IVC stand-by state, and generates an internal voltage.

Abstract: A mixed mode smart card is disclosed including an internal circuit having a CPU, a contactless mode processor adapted to prosecute a contactless mode operation, and a contact mode processor adapted to prosecute a contact mode operation. The mixed mode smart card also includes a power voltage control block receiving contact and contactless mode power source voltages and supplying the internal circuit with an internal power source voltage derived either during an entire period of mixed mode operation.

Abstract: A shadow mask for a Cathode Ray Tube (CRT) facilitates high resolution with enhanced impact resistance and minimized thickness. The shadow mask has an effective screen portion with a plurality of beam passage holes arranged in a predetermined pattern, and a non-holed portion surrounding the effective screen portion with no beam passage holes., The vertical pitch of the beam passage holes is in the range of 0.4-0.5 mm, and the thickness of the shadow mask is in the range of 0.15-0.2 mm.

Abstract: A mixed mode smart card is disclosed including an internal circuit having a CPU, a contactless mode processor adapted to prosecute a contactless mode operation, and a contact mode processor adapted to prosecute a contact mode operation. The mixed mode smart card also comprises a power voltage control block receiving contact and contactless mode power source voltages and supplying the internal circuit with an internal power source voltage derived either during an entire period of mixed mode operation.

Abstract: A voltage-glitch detection circuit includes a voltage comparator having two input terminals with different capacitance resistance charge/discharge time. Voltage dividers are coupled to the two input terminals of the voltage comparator respectively, and commonly receive a supply voltage. One of the voltage dividers is supplied to the voltage comparator as a reference voltage of the voltage comparator, and the other is supplied as a glitch detection voltage to the voltage comparator.

Abstract: A cathode ray tube includes a color selection apparatus mounted between a phosphor screen and an electron gun, and support members for supporting the color selection apparatus. Each of the support members is formed by a spring including a fixed section secured to the color selection apparatus, a locking section connected to the cathode ray tube, and a center section formed between these elements. The fixed section and the center section are separated by and bent at a first folding trace, and the center section and the locking section are separated by and bent at a second folding trace. Also, if a direction along a width of the springs is X, the first folding trace has an angle ?1 with a straight line drawn on the fixed section along direction X, and the second folding trace has an angle ?2 with a straight line drawn on the center section along direction X, the angle ?2 is greater than the angle ?1.

Abstract: Provided is a smart card for communicating with a host computer through a universal serial bus (USB). The smart card includes an internal clock signal generator to generate an internal clock signal, a period detector to detect a period of the internal clock signal and to generate a control code according to the detected period, and a transmission clock generator to generate a transmission clock signal which varies from the internal clock signal according to the control code. The smart card transfers data in sync with the transmission clock signal.

Abstract: A cathode ray tube includes a panel having a substantially flat outer surface and an inner curved surface with a phosphor screen. The panel has a substantially rectangular effective screen portion with two long sides parallel to each other, two short sides parallel to each other and four rounded edges interconnecting each long side and the neighboring short side. The effective screen portion is structure such that a first line V1 interconnecting centers of the long sides, a second line H1 interconnecting centers of the short sides and a third line D1 interconnecting centers of the rounded edges opposite to each other meet at a point. The effective screen portion has a first thickness Tv at the centers of the long sides, a second thickness Th at the centers of the short sides, a third thickness Td at the centers of the edges and a fourth thickness Tc at the meeting point of the all three lines V1, H1 and D1.