Abstract: An apparatus and method for assigning a Physical Cell Identity (PCI) of a Home eNodeB (HeNB) are provided. The apparatus may distribute PCIs into a plurality of PCI groups, and may enable a PCI group to be assigned to a cell so that the assigned PCI group may be different from a PCI group assigned to a neighboring cell, and that an unassigned PCI in the assigned PCI group may be assigned to an HeNB within a single cell.

Abstract: Provided is a method and apparatus for avoiding a collision of a preamble in a base station. When a new base station is installed in a mobile communication system and in this instance, an exclusive preamble using a contention-free scheme is employed to avoid a preamble collision, at least one of a code parameter, a time parameter, and a frequency parameter used in a preamble of the new base station may be set to be different from a code parameter, a time parameter, and a frequency parameter used in a preamble of a neighboring cell, whereby it is possible to manage a random access preamble without causing a collision between cells.

Abstract: An apparatus for managing components in an SCA system includes a naming context tree having one or more directories. Each directory has an ID, the ID is assigned to a component to be registered, and the component is registered in the directory having the ID and unregistered from the directory. The apparatus further includes a name server for managing the components registered in the directories of the naming context tree.

Abstract: An apparatus for driving a loadable device component, the apparatus including: the loadable device component providing an application with a loading mechanism that is classified according to a load type property; a core framework module component defining a kind of the load type property; at least one eXtensible Markup Language (XML) data component containing configuration information and generation information of the loadable device component; and a device manager component driving a corresponding loadable device component after parsing the XML data component.

Abstract: Provided is a method of manufacturing a wafer carrier capable of providing good abrasion resistance to remarkably increase lifespan of the wafer carrier, and preventing occurrence of defects from an edge of a wafer during double-sided polishing of the wafer. The method includes machining a carrier body constituting the wafer carrier in a pre-set shape, forming a preliminary hole and a slurry introduction hole in the carrier body of the wafer carrier, coating diamond-like carbon (DLC) on the carrier body having the preliminary hole, and, after coating the DLC, enlarging the preliminary hole to form a wafer retaining hole, into which the wafer is inserted.

Abstract: A semiconductor memory device comprises a local sense amplifier connected between a bit line sense amplifier and a current sensing type input/output (IO) sense amplifier. The bit line sense amplifier is connected between a bit line pair, the bit line pair is connected to a local data IO pair, and the local data IO pair is connected to a global data IO pair via a pair of switching circuits. During a read operation of the semiconductor memory device, the local data IO pair remains connected to the global data IO pair.

Abstract: A delay-locked loop circuit comprising a variable voltage generator and a delay-locked loop. The variable voltage generator is configured to generate a variable bias voltage signal in response to a standby signal. The variable bias voltage signal has differing voltage levels according to operation modes. The operation modes include a standby mode and an active mode. The delay-locked loop is configured to generate an internal clock signal in response to the standby signal and the variable bias voltage signal. The internal clock signal is synchronized with an external clock signal.

Abstract: An application component communication method and an apparatus using the same are provided to an SCA-based system for efficiently performing data communication between SCA-based application components by using a dynamic connection manager. The application component communication apparatus includes an application module provided in the SCA-based system and driven, an application packaged by a plurality of application components, and an application factory for generating the application and driving the application components by parsing XML files. The dynamic connection manager registers port information of each of the application components, and establishes a connection for data communication between the application components according to the port information. According to the present invention, data communication between the respective application components can be efficiently performed by using the dynamic connection manager.

Abstract: A semiconductor memory device comprises a local sense amplifier connected between a bit line sense amplifier and a current sensing type input/output (IO) sense amplifier. The bit line sense amplifier is connected between a bit line pair, the bit line pair is connected to a local data IO pair, and the local data IO pair is connected to a global data IO pair via a pair of switching circuits. During a read operation of the semiconductor memory device, the local data IO pair remains connected to the global data IO pair.

Abstract: A delay-locked loop circuit comprising a variable voltage generator and a delay-locked loop. The variable voltage generator is configured to generate a variable bias voltage signal in response to a standby signal. The variable bias voltage signal has differing voltage levels according to operation modes. The operation modes include a standby mode and an active mode. The delay-locked loop is configured to generate an internal clock signal in response to the standby signal and the variable bias voltage signal. The internal clock signal is synchronized with an external clock signal.

Abstract: A semiconductor memory device having a data read path maintains a higher power voltage supplied to an input/output sense amplifier in the input/output path, through which data passes during a data read operation, than the voltage supplied to other circuit components in the data read path, thereby achieving a high data read speed.

Abstract: A semiconductor memory device having a data read path maintains a higher power voltage supplied to an input/output sense amplifier in the input/output path, through which data passes during a data read operation, than the voltage supplied to other circuit components in the data read path, thereby achieving a high data read speed.

Abstract: A memory charging circuit includes a read charge control circuit controlled according to a read control signal and an address value. A write charge control circuit is controlled according to a write control signal and the same or a different address value. Charging to and charging from the same data IO lines is controlled using the read charge amplifier circuit and the write charge amplifier circuit. A column select line circuit can be configured into a first arrangement where a first output is activated according to a read control signal and an address and a second output is activated according to a write control signal and the same or a different address. In a second arrangement, the first output is activated according to an address and either the read control signal or the write control signal.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks each including a plurality of partial blocks, a plurality of global word lines, and odd-numbered and even-numbered sub word lines corresponding to each of the plurality of the global word lines, the odd-numbered sub word lines of each of odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the previous neighboring partial blocks, the even-numbered sub word lines of each of the odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the even-numbered sub word lines of each of the next neighboring partial blocks, the odd-numbered sub word lines of each of even-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the next neighboring partial blocks, the even-numbered sub word lines of each of the even-numbered partial blocks

Abstract: A semiconductor memory device capable of improving common bus efficiency is disclosed. The device comprises an address shifting circuit for delaying an address by an n+m number of clock cycles in response to a clock signal, a control signal generating circuit for combining a column address strobe (CAS) latency of n-value and one of first and second operation signals to generate a control signal, and a switching circuit for outputting the address delayed by the n+m number of clock cycles output from the address shifting circuit in response to the control signal. The first operation signal indicates that the n-value of the CAS latency is less than a predetermined value and write latency is fixed. The second operation signal indicates that the n-value of the CAS latency is equal to or greater than the predetermined value and the write latency is variable.

Abstract: A semiconductor memory device capable of improving common bus efficiency is disclosed. The device comprises an address shifting circuit for delaying an address by an n+m number of clock cycles in response to a clock signal, a control signal generating circuit for combining a column address strobe (CAS) latency of n-value and one of first and second operation signals to generate a control signal, and a switching circuit for outputting the address delayed by the n+m number of clock cycles output from the address shifting circuit in response to the control signal. The first operation signal indicates that the n-value of the CAS latency is less than a predetermined value and write latency is fixed. The second operation signal indicates that the n-value of the CAS latency is equal to or greater than the predetermined value and the write latency is variable.

Abstract: A memory charging circuit includes a read charge control circuit controlled according to a read control signal and an address value. A write charge control circuit is controlled according to a write control signal and the same or a different address value. Charging to and charging from the same data IO lines is controlled using the read charge amplifier circuit and the write charge amplifier circuit. A column select line circuit can be configured into a first arrangement where a first output is activated according to a read control signal and an address and a second output is activated according to a write control signal and the same or a different address. In a second arrangement, the first output is activated according to an address and either the read control signal or the write control signal.

Abstract: A memory charging circuit includes a read charge control circuit controlled according to a read control signal and an address value. A write charge control circuit is controlled according to a write control signal and the same or a different address value. Charging to and charging from the same data IO lines is controlled using the read charge amplifier circuit and the write charge amplifier circuit. A column select line circuit can be configured into a first arrangement where a first output is activated according to a read control signal and an address and a second output is activated according to a write control signal and the same or a different address. In a second arrangement, the first output is activated according to an address and either the read control signal or the write control signal.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks each including a plurality of partial blocks, a plurality of global word lines, and odd-numbered and even-numbered sub word lines corresponding to each of the plurality of the global word lines, the odd-numbered sub word lines of each of odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the previous neighboring partial blocks, the even-numbered sub word lines of each of the odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the even-numbered sub word lines of each of the next neighboring partial blocks, the odd-numbered sub word lines of each of even-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the next neighboring partial blocks, the even-numbered sub word lines of each of the even-numbered partial blocks

Abstract: A buffer includes a pull-down means, a pull-up means, and a control signal generator. The pull-down means generates an output signal that transitions to a first state at a relatively high speed when an input signal transitions from a first state to a second state in response to a control signal at a first control state. The pull-up means generates an output signal that transitions to the second state at a relatively high speed when an input signal transitions from the second state to the first state in response to a control signal of a second control state. The control signal generator produces the control signal as a function of the output signal. Accordingly, the buffer can transfer an input signal at a high speed in both cases of a high-to-low transition of the input signal as well as a low-to-high transition of the input signal.