Patents by Inventor Chan Yoo

Chan Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250117940
    Abstract: The present disclosure relates to a method, performed by at least one processor of an information processing system, of analyzing a pathological image. The method includes receiving a pathological image, detecting an object associated with medical information, in the received pathological image by using a machine learning model, generating an analysis result on the received pathological image, based on a result of the detecting, and outputting medical information about at least one region included in the pathological image, based on the analysis result.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 10, 2025
    Applicant: Lunit Inc.
    Inventors: Chan-Young OCK, Donggeun YOO, Kyunghyun PAENG
  • Publication number: 20250107337
    Abstract: Provided is a display panel including a base substrate, a display element layer, and a light control layer, wherein the display element layer includes a first electrode, a second electrode, a light-emitting layer and a first pixel definition layer, the light control layer includes a second pixel definition layer, and a light control pattern including quantum dots, a bottom surface of the first pixel definition layer has a first width in a first direction, the first pixel definition layer has a first height in a second direction, a bottom surface of the second pixel definition layer has a second width in the first direction, the second pixel definition layer has a second height in the second direction, and a first aspect ratio calculated by dividing the first height by the first width is smaller than a second aspect ratio calculated by dividing the second height by the second width.
    Type: Application
    Filed: March 27, 2024
    Publication date: March 27, 2025
    Inventors: Byoung-Hwa KWON, Chan-mo KANG, Hyungwoo SUH, Jin Wook SHIN, YOONSUNG YOO, Hyunsu CHO, Chul Woong JOO, Sukyung CHOI
  • Publication number: 20250105301
    Abstract: Provided is a collector including an adhesion enhancing layer capable of providing a positive electrode having excellent adhesion and low interfacial resistance, a positive electrode including the same, and a lithium secondary battery including the positive electrode. The collector includes a conductive metal layer, and an adhesion enhancing layer provided on at least one surface of the conductive metal layer, wherein the adhesion enhancing layer has a surface roughness (Ra) of 90 nm to 600 nm and a diiodomethane contact angle of 70° to 120°.
    Type: Application
    Filed: January 13, 2023
    Publication date: March 27, 2025
    Applicants: LG Chem, Ltd., LG Energy Solution, Ltd.
    Inventors: Jung Hyun Seo, Min Soo Kim, Dong Oh Shin, Ho Chan Lee, Kwang Ho Yoo, Soon Hwa Jung
  • Patent number: 12260043
    Abstract: A method of driving an electronic device includes displaying a plurality of fingerprint recognition icons on a display device configured to perform fingerprint recognition, and releasing a lock state of the display device through a fingerprint authentication process upon determining at least one first fingerprint recognition icon among the plurality of fingerprint recognition icons is touched. The plurality of fingerprint recognition icons include at least one first fingerprint recognition icon configured to support the fingerprint recognition and at least one second fingerprint recognition icon configured to not support the fingerprint recognition.
    Type: Grant
    Filed: September 8, 2023
    Date of Patent: March 25, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byung Han Yoo, Jung Woo Park, Hyang A Park, Dae Young Lee, Hyun Dae Lee, Kang Bin Jo, Sang Hwan Cho, Sung-Chan Jo
  • Publication number: 20250081445
    Abstract: A semiconductor memory device includes a bit line extending in a first direction on a substrate, an active pattern on the bit line, a word line on a first sidewall of the active pattern and extending in a second direction, a back gate electrode on a second sidewall of the active pattern and extending in the second direction, a gate isolation pattern on the first sidewall of the active pattern and including a low-k pattern extending in the second direction, and a data storage pattern connected to the second surface of the active pattern. The word line is between the active pattern and the gate isolation pattern, and a vertical distance between the bit line and the word line is greater than a vertical distance between the bit line and the low-k pattern.
    Type: Application
    Filed: May 10, 2024
    Publication date: March 6, 2025
    Inventors: Bo Won Yoo, Seok Han Park, Keun Ui Kim, Yu Jin Kim, Joong Chan Shin, Gyu Hwan Oh, Eun Suk Jang, Jin Woo Han
  • Publication number: 20250029707
    Abstract: The present disclosure relates to a medical image analysis method using a processor and a memory which are hardware. The method includes generating predicted second metadata for a medical image by using a prediction model, and determining a processing method of the medical image based on one of first metadata stored corresponding to the medical image and the second metadata.
    Type: Application
    Filed: October 4, 2024
    Publication date: January 23, 2025
    Inventors: Jong Chan PARK, Dong Geun YOO, Ki Hyun YOU, Hyeon Seob NAM, Hyun Jae LEE, Sang Hyup LEE
  • Patent number: 12205288
    Abstract: The present disclosure relates to a method, performed by at least one processor of an information processing system, of analyzing a pathological image. The method includes receiving a pathological image, detecting an object associated with medical information, in the received pathological image by using a machine learning model, generating an analysis result on the received pathological image, based on a result of the detecting, and outputting medical information about at least one region included in the pathological image, based on the analysis result.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: January 21, 2025
    Assignee: Lunit Inc.
    Inventors: Chan-Young Ock, Donggeun Yoo, Kyunghyun Paeng
  • Publication number: 20230020689
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.
    Type: Application
    Filed: September 23, 2022
    Publication date: January 19, 2023
    Inventors: Chan Yoo, Todd O. Bolken
  • Patent number: 11456286
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chan Yoo, Todd O. Bolken
  • Patent number: 11285532
    Abstract: Provided are a boron-nitride nanoplatelet(s) (BNNP)/metal nanocomposite powder and a preparing method thereof, the BNNP/metal nanocomposite powder including a base metal and BNNP dispersed in the base metal and configured to serve as a reinforcement of the base metal, wherein the BNNP are interposed between metal particles of the base metal in the form of a thin film of a plurality of layers and combined with the metal particles, and an amount of the BNNP in the base metal is greater than 0 vol % and less than 90 vol %.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: March 29, 2022
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Soon Hyung Hong, Sung Chan Yoo, Jun Ho Lee, Hee Su Byeon
  • Patent number: 11034801
    Abstract: The present invention provides a method for preparing a transparent hydrogel membrane, the method including: (a) preparing 6 to 10 wt % of a hyaluronic acid solution based on a total weight of a mixture by dissolving a hyaluronic acid in a basic aqueous solution; (b) mixing, with the hyaluronic acid solution, 0.01 to 0.05 wt % of a crosslinking agent based on the total weight of the mixture; and (c) shaping the transparent hydrogel membrane by pouring the mixture into a mold.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 15, 2021
    Assignee: JCBIO CO., LTD.
    Inventors: Jae Chan Yoo, Yoo Lee Kang, Min Young Kong
  • Publication number: 20200269314
    Abstract: Provided are a boron-nitride nanoplatelet(s) (BNNP)/metal nanocomposite powder and a preparing method thereof, the BNNP/metal nanocomposite powder including a base metal and BNNP dispersed in the base metal and configured to serve as a reinforcement of the base metal, wherein the BNNP are interposed between metal particles of the base metal in the form of a thin film of a plurality of layers and combined with the metal particles, and an amount of the BNNP in the base metal is greater than 0 vol % and less than 90 vol %.
    Type: Application
    Filed: January 23, 2019
    Publication date: August 27, 2020
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Soon Hyung HONG, Sung Chan YOO, Jun Ho LEE, Hee Su BYEON
  • Publication number: 20200262985
    Abstract: The present invention provides a method for preparing a transparent hydrogel membrane, the method including: (a) preparing 6 to 10 wt % of a hyaluronic acid solution based on a total weight of a mixture by dissolving a hyaluronic acid in a basic aqueous solution; (b) mixing, with the hyaluronic acid solution, 0.01 to 0.05 wt % of a crosslinking agent based on the total weight of the mixture; and (c) shaping the transparent hydrogel membrane by pouring the mixture into a mold.
    Type: Application
    Filed: September 18, 2018
    Publication date: August 20, 2020
    Inventors: Jae Chan YOO, Yoo Lee KANG, Min Young KONG
  • Publication number: 20200243493
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.
    Type: Application
    Filed: April 6, 2020
    Publication date: July 30, 2020
    Inventors: Chan Yoo, Todd O. Bolken
  • Patent number: 10615154
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chan Yoo, Todd O. Bolken
  • Publication number: 20200075548
    Abstract: Systems, devices, and methods for interconnects for a multi-die package are described. A multi-die package may include a set of conductive pillars and two or more semiconductor dice that each include a bond pad. In some cases, the multi-die package may include a plurality of pillar-wire combinations, and a bond wire may couple a corresponding conductive pillar with a corresponding bond pad. Pillar-wire combinations may each collectively have a matched impedance, or pillar-wire combinations in different groups may have different collective impedances. In other cases, a conductive pillar may be directly coupled with a corresponding bond pad without a bond wire. Different pillar-wire combinations or directly-coupled pillars may carry different signals. In some cases, pillars may be individually impedance-matched to a desired impedance.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 5, 2020
    Inventors: Kang-Yong Kim, Chan Yoo, Dong Soon Lim, Jaekyu Song
  • Patent number: 10366934
    Abstract: A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides of the first and second dies may each face the interposer. A bond wire may electrically connect the first die to the second side of the interposer and a bond wire may electrically connect the second die to the first side of the interposer. The bond wires may extend through a plurality of windows in the interposer. First and second dies may be attached to a first side of an interposer and may be electrically connected to a second side of the interposer through windows and third and fourth dies may be attached to a second side of the interposer and may be electrically connected to the first side of the interposer through windows.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chan Yoo, Akshay Singh, Yi Xu, Liana Foster, Steven Eskildsen
  • Publication number: 20190088565
    Abstract: A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides of the first and second dies may each face the interposer. A bond wire may electrically connect the first die to the second side of the interposer and a bond wire may electrically connect the second die to the first side of the interposer. The bond wires may extend through a plurality of windows in the interposer. First and second dies may be attached to a first side of an interposer and may be electrically connected to a second side of the interposer through windows and third and fourth dies may be attached to a second side of the interposer and may be electrically connected to the first side of the interposer through windows.
    Type: Application
    Filed: November 20, 2018
    Publication date: March 21, 2019
    Inventors: Chan Yoo, Akshay Singh, Yi Xu, Liana Foster, Steven Eskildsen
  • Publication number: 20180358275
    Abstract: A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides of the first and second dies may each face the interposer. A bond wire may electrically connect the first die to the second side of the interposer and a bond wire may electrically connect the second die to the first side of the interposer. The bond wires may extend through a plurality of windows in the interposer. First and second dies may be attached to a first side of an interposer and may be electrically connected to a second side of the interposer through windows and third and fourth dies may be attached to a second side of the interposer and may be electrically connected to the first side of the interposer through windows.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 13, 2018
    Inventors: Chan Yoo, Akshay Singh, Yi Xu, Liana Foster, Steven Eskildsen
  • Patent number: 10153221
    Abstract: A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides of the first and second dies may each face the interposer. A bond wire may electrically connect the first die to the second side of the interposer and a bond wire may electrically connect the second die to the first side of the interposer. The bond wires may extend through a plurality of windows in the interposer. First and second dies may be attached to a first side of an interposer and may be electrically connected to a second side of the interposer through windows and third and fourth dies may be attached to a second side of the interposer and may be electrically connected to the first side of the interposer through windows.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 11, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Chan Yoo, Akshay Singh, Yi Xu, Liana Foster, Steven Eskildsen