Patents by Inventor Chan Yuan Chen

Chan Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5942785
    Abstract: An integrated circuit device having a reduced buried contact resistance is achieved. A gate electrode lies on the surface of a semiconductor substrate. Source/drain regions within the semiconductor substrate surround the gate electrode. A polysilicon contact lies on the surface of the semiconductor substrate. A buried contact junction underlies the polysilicon contact and adjoins one of the source/drain regions. A doped polysilicon layer partially fills a trench in the semiconductor substrate at the junction between the buried contact junction and one of the source/drain regions wherein the doped polysilicon layer provides a conduction channel between the source/drain region and the adjoining buried contact junction.
    Type: Grant
    Filed: April 18, 1997
    Date of Patent: August 24, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan Yuan Chen, Shih Bin Peng
  • Patent number: 5745405
    Abstract: A method and an apparatus for the measurement and evaluation of leakage currents within an SRAM cell is described. The leakage current is present in the cutoff device of a cross coupled pair of field effect transistors in a four transistor SRAM cell. Each of the load resistors of the SRAM cell is connected through a pass gate to a chain of high value resistances to the contact structure that is connected to a power supply voltage source. An expected value of leakage current is less than the quotient of the difference of the magnitude of the power supply voltage source and the threshold voltage of the cutoff field effect transistor of the cross coupled pair of field effect transistors, and the summation of the ohmic value of the load resistor of the SRAM cell and the ohmic value of all the resistors in the chain of high value resistance between the contact structure and the pass gate connecting the SRAM cell to the chain of high value resistances.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: April 28, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, LTD
    Inventors: Chan Yuan Chen, Kao Min Chi
  • Patent number: 5668051
    Abstract: A new method of forming improved buried contact junctions is described. A first layer of polysilicon is deposited overlying a gate silicon oxide layer on a semiconductor substrate. These layers are etched away to provide an opening to the semiconductor substrate where the planned buried contact junction will be formed. A second polysilicon layer is deposited overlying the first polysilicon layer and the planned buried contact junction. Dopant is driven in from the second polysilicon layer to form the buried contact junction. The second polysilicon layer is etched away to provide a polysilicon contact overlying the buried contact junction and providing an opening to the semiconductor substrate where a planned source/drain region will be formed adjacent to the buried contact junction wherein a portion of the second polysilicon layer remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the buried contact junction.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: September 16, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan Yuan Chen, Shih Bin Peng