Patents by Inventor Chanaka MUNASINGHE

Chanaka MUNASINGHE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240404917
    Abstract: Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.
    Type: Application
    Filed: June 1, 2023
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventors: Sikandar Abbas, Chanaka Munasinghe, Leonard Guler, Reza Bayati, Madeleine Stolt, Makram Abd El Qader, Pratik Patel, Anindya Dasgupta
  • Publication number: 20230320057
    Abstract: Integrated circuit (IC) devices include transistors with gate, source and drain contact metallization, some of which are jumpered together by a metallization that is recessed below a height of other metallization that is not jumpered. The jumper metallization may provide a local interconnect between terminals of one transistor or adjacent transistors, for example between a gate of one transistor and a source/drain of another transistor. The jumper metallization may not induce the same pitch constraints faced by interconnect line metallization levels employed for more general interconnection. In some examples, a static random-access memory (SRAM) bit-cell includes a jumper metallization joining two transistors of the cell to reduce cell height for a given feature patterning capability.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Applicant: Intel Corporation
    Inventors: Clifford Ong, Leonard Guler, Mohit Haran, Smita Shridharan, Reken Patel, Charles Wallace, Chanaka Munasinghe, Pratik Patel
  • Publication number: 20230101725
    Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprises silicon, and germanium that at least partially covers the epitaxial source or drain structures. A conductive contact comprising titanium silicide is on the epitaxial source or drain structures.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Debaleena NANDI, Mauro J. KOBRINSKY, Gilbert DEWEY, Chi-hing CHOI, Harold W. Kennel, Brian J. KRIST, Ashkar ALIYARUKUNJU, Cory BOMBERGER, Rushabh SHAH, Rishabh MEHANDRU, Stephen M. CEA, Chanaka MUNASINGHE, Anand S. MURTHY, Tahir GHANI
  • Publication number: 20220399373
    Abstract: An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.
    Type: Application
    Filed: June 15, 2021
    Publication date: December 15, 2022
    Inventors: Leonard P. GULER, Chanaka MUNASINGHE, Makram ABD EL QADER, Marie CONTE, Saurabh MORARKA, Elliot N. TAN, Krishna GANESAN, Mohit K. HARAN, Charles H. WALLACE, Tahir GHANI, Sean PURSEL
  • Patent number: 10090304
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area. In further embodiments, the impurity source film may provide a source of dopant that renders the sub-fin region complementarily doped relative to a region of the substrate forming a P/N junction that is at least part of an isolation structure electrically isolating the active fin region from a region of the substrate.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan, Jeng-Ya D. Yeh, Hsu-Yu Chang, Neville Dias, Chanaka Munasinghe
  • Publication number: 20160211262
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area. In further embodiments, the impurity source film may provide a source of dopant that renders the sub-fin region complementarily doped relative to a region of the substrate forming a P/N junction that is at least part of an isolation structure electrically isolating the active fin region from a region of the substrate.
    Type: Application
    Filed: September 25, 2013
    Publication date: July 21, 2016
    Inventors: Walid M. HAFEZ, Chia-Hong JAN, Jeng-Ya D. YEH, Hsu-Yu CHANG, Neville DIAS, Chanaka MUNASINGHE