Patents by Inventor Chandan AGARWALLA

Chandan AGARWALLA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11880454
    Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: January 23, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Bharat Kumar Rangarajan, Dipti Ranjan Pal, Keith Alan Bowman, Srinivas Turaga, Ateesh Deepankar De, Shih-Hsin Jason Hu, Chandan Agarwalla
  • Patent number: 11493970
    Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 8, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Kong Yee Chun, Chandan Agarwalla, Dipti Ranjan Pal, Kumar Kanti Ghosh, Matthew Severson, Nilanjan Banerjee, Joshua Stubbs
  • Publication number: 20220137687
    Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Inventors: Christopher Kong Yee CHUN, Chandan AGARWALLA, Dipti Ranjan PAL, Kumar Kanti GHOSH, Matthew SEVERSON, Nilanjan BANERJEE, Joshua STUBBS
  • Publication number: 20210357502
    Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.
    Type: Application
    Filed: May 14, 2020
    Publication date: November 18, 2021
    Inventors: Bharat Kumar RANGARAJAN, Dipti Ranjan PAL, Keith Alan BOWMAN, Srinivas TURAGA, Ateesh Deepankar DE, Shih-Hsin Jason HU, Chandan AGARWALLA