Abstract: An integrated circuit (IC), including a recording circuit and a clocking system, is provided. During a capture phase of an at-speed testing of the IC, the recording circuit records a number of clock pulses of a test clock signal and generates configuration data indicative of the recorded number of the clock pulses. The clocking system receives a reference clock signal and the configuration data and generates an at-speed clock signal. During the capture phase, the at-speed clock signal includes clock pulses that are extracted from the reference clock signal based on the configuration data. A count of the extracted clock pulses is equal to the recorded number of clock pulses of the test clock signal. The at-speed testing of the IC is enabled based on the at-speed clock signal.

Abstract: Aspects of the subject disclosure may include, for example, monitoring first data to identify a first plurality of test points, analyzing the first plurality of test points to identify the first data as being associated with a first time domain included in a plurality of time domains, wherein respective portions of a device under test (DUT) are operative in accordance with a given time domain included in the plurality of time domains, and based on the analyzing of the first plurality of test points, generating first control signals to cause a first clock signal to be adapted to generate a second clock signal that is different from the first clock signal.

Abstract: An apparatus and method are provided for scan testing a system-on-chip (SoC) integrated circuit having first and second partitions coupled together across one or more inter-partition circuits, each of which includes a decompressor; a compactor; an INTEST scan chain and an EXTEST scan chain coupled in parallel between the decompressor circuit and compactor circuit; and digital test control access hardware connected between the decompressor circuit and each INTEST scan chain and configured to selectively disable each INTEST scan chain while each EXTEST scan chain continues to operate in response to a partition EXTEST mode signal having a first predetermined value.

Abstract: An integrated circuit (IC), including a clocking system, a plurality of clock gate controllers, and a plurality of clock gates, is provided. During a capture phase of an at-speed testing of the IC, the clocking system generates an at-speed clock signal including launch and capture pulses that are extracted from a reference clock signal based on a capture phase frequency. The plurality of clock gate controllers generates a plurality of enable signals such that for the launch pulse, one enable signal is asserted, and for the capture pulse, the same or different enable signal is asserted. Each of the plurality of clock gates is activated based on an assertion of a corresponding enable signal. Further, during the capture phase, one or more activated clock gates enable the at-speed testing of the IC based on the at-speed clock signal.

Abstract: An integrated circuit (IC) includes power domains and I/O multiplexing units. The I/O multiplexing units include components that are spilt across the power domains. The I/O multiplexing units multiplex signals received from the power domains and provide signals to one or more peripheral devices connected to the IC by way of I/O pads of the IC.

Abstract: A safety device with an error indication function includes at least one ERROR pad configured between the error indication function and at least one normal function, and a set of multiplexers connected to the ERROR pad. The safety device further includes an error indication block and a functional block multiplexed by the set of multiplexers. The error indication block includes a fault collection and control unit for collecting and providing error occurrence information to the ERROR pad, and an ERROR pad select control register for storing ERROR pad selection and configuration information to control select inputs of the first set of multiplexers and provide the ERROR pad configuration information to the ERROR pad.

Abstract: A programming interface and method of operating a programming interface use a system clock input, an asynchronous reset input, and an interface control input. The method selectively controls multiplexed coupling of a source register to a destination register and the destination register to a buffer register. The multiplexed coupling of the destination register to the buffer register reduces the possibility of the buffer register being corrupted when an asynchronous reset signal is applied to the programming interface. Problems associated with meta-stable asynchronous crossing paths in asynchronous reset programming systems are therefore alleviated.

Abstract: A safety device with an error indication function includes at least one ERROR pad configured between the error indication function and at least one normal function, and a set of multiplexers connected to the ERROR pad. The safety device further includes an error indication block and a functional block multiplexed by the set of multiplexers. The error indication block includes a fault collection and control unit for collecting and providing error occurrence information to the ERROR pad, and an ERROR pad select control register for storing ERROR pad selection and configuration information to control select inputs of the first set of multiplexers and provide the ERROR pad configuration information to the ERROR pad.

Abstract: A programming interface and method of operating a programming interface use a system clock input, an asynchronous reset input, and an interface control input. The method selectively controls multiplexed coupling of a source register to a destination register and the destination register to a buffer register. The multiplexed coupling of the destination register to the buffer register reduces the possibility of the buffer register being corrupted when an asynchronous reset signal is applied to the programming interface. Problems associated with meta-stable asynchronous crossing paths in asynchronous reset programming systems are therefore alleviated.

Abstract: A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.

Abstract: A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.