Patents by Inventor Chandan Hks

Chandan Hks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9612907
    Abstract: Tasks may be scheduled on more than one processor to allow the processors to operate at lower processor frequencies and processor supply voltages. Multiple processors executing tasks in parallel at lower frequencies and supply voltages may allow completion of the tasks by deadlines at lower power consumption than a single processor executing all tasks at high frequencies and supply voltages. Power efficiency of a computer system may be improved by using a combination of processors executing tasks using a combination of earliest deadline first (EDF), earliest deadline last (EDL), and round robin (RR) queue management methods.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: April 4, 2017
    Assignee: Unisys Corporation
    Inventors: Chandan Hks, Sonika P Reddy
  • Publication number: 20150378782
    Abstract: Tasks may be scheduled on more than one processor to allow the processors to operate at lower processor frequencies and processor supply voltages. In particular, realtime tasks may be scheduled on idle processors without context switching an existing executing tasks. For example, a method of executing tasks on a plurality of processors may include receiving a new task with an earlier deadline than an executing task; determining whether an idle processor is available; and when an idle processor is available, executing the new task on the idle processor.
    Type: Application
    Filed: November 17, 2014
    Publication date: December 31, 2015
    Applicant: Unisys Corporation
    Inventors: Chandan Hks, Sonika P. Reddy
  • Publication number: 20150242275
    Abstract: Tasks may be scheduled on more than one processor to allow the processors to operate at lower processor frequencies and processor supply voltages. Multiple processors executing tasks in parallel at lower frequencies and supply voltages may allow completion of the tasks by deadlines at lower power consumption than a single processor executing all tasks at high frequencies and supply voltages. Power efficiency of a computer system may be improved by using a combination of processors executing tasks using a combination of earliest deadline first (EDF), earliest deadline last (EDL), and round robin (RR) queue management methods.
    Type: Application
    Filed: November 17, 2014
    Publication date: August 27, 2015
    Applicant: Unisys Corporation
    Inventors: Chandan Hks, Sonika P. Reddy