Abstract: An example method is disclosed, the method comprising: (i) detecting, via a first sensor of an alert system configured for use with a vehicle, a living being inside the vehicle; (ii) measuring, via a second sensor, an environmental feature inside the vehicle; (iii) based at least on the detection of the living being and the measured environmental feature, determining, an alert condition inside the vehicle; (iv) selecting a first computational action based at least on the determined alert condition; (v) transmitting an instruction that causes a component of the vehicle to perform the selected first computational action; (vi) selecting a second computational action based at least on the determined alert condition; and (vii) transmitting, via a network interface, to at least one computing device that is remote from the alert system, an instruction that causes at least one remote computing device to perform the selected second computational action.

Abstract: Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.

Abstract: An example method is disclosed, the method comprising: (i) detecting, via a first sensor of an alert system configured for use with a vehicle, a living being inside the vehicle; (ii) measuring, via a second sensor, an environmental feature inside the vehicle; (iii) based at least on the detection of the living being and the measured environmental feature, determining, an alert condition inside the vehicle; (iv) selecting a first computational action based at least on the determined alert condition; (v) transmitting an instruction that causes a component of the vehicle to perform the selected first computational action; (vi) selecting a second computational action based at least on the determined alert condition; and (vii) transmitting, via a network interface, to at least one computing device that is remote from the alert system, an instruction that causes at least one remote computing device to perform the selected second computational action.

Abstract: Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to group physical addresses of the set of non-volatile memory cells into groups of configurable sizes and to individually apply wear leveling schemes to non-volatile memory cells of a group.

Abstract: Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for error reducing matrix generation. An apparatus includes a test circuit that performs a test on a set of memory cells. An apparatus includes a masking circuit that determines a masking array based on a test performed on a set of memory cells. An apparatus includes a decoding circuit that decodes encoded data from a set of memory cells based on a masking array.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to map the set of non-volatile memory cells into a plurality of regions, apply a first wear leveling scheme in a first region of the plurality of regions, and apply a second wear leveling scheme between the plurality of regions.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for redundant array of independent disks (RAID) stripe physical placement. An apparatus includes a plurality of memory die comprising physical pages for storing data. An apparatus includes a control circuit that assigns addresses to a plurality of data stripes, wherein the control circuit assigns the addresses to the plurality of data stripes by: assigning stripe pages of a data stripe of the plurality of data stripes to different memory die of a plurality of memory die; and assigning adjacent stripe pages of the data stripe to different page numbers.

Abstract: Apparatuses, systems, and methods are disclosed for mapping-based wear leveling for non-volatile memory. An apparatus may include one or more non-volatile memory elements, and a controller. A controller may maintain a logical-to-physical mapping for converting logical addresses to physical addresses. A logical-to-physical mapping may include a translation table that associates groups of logical addresses with groups of physical addresses, and one or more mathematical mappings. A mathematical mapping for a group of logical addresses may associate individual logical addresses within the group of logical addresses with individual physical addresses within a corresponding group of physical addresses. A controller may change at least one mathematical mapping. A controller may move data based on at least one changed mapping.

Abstract: Aspects of the present disclosure provide systems and methods for operating a solid state drive (SSD) using two-level indirection architecture. The SSD receives a command to perform a data operation in a NAND array and a logical address for the data operation. The SSD then converts the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table that includes a first stage stored in a byte-rewritable memory and a second stage stored in a block-erasable non-volatile memory (NVM). The SSD performs the data operation in the NAND array based on the physical address. The byte-rewritable memory may any byte-rewritable persistent memory. The block-erasable low latency NVM may be a flash memory that has lower latency than NAND array.

Abstract: Aspects of the present disclosure provide systems and methods for operating a solid state drive (SSD) using two-level indirection architecture. The SSD receives a command to perform a data operation in a NAND array and a logical address for the data operation. The SSD then converts the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table that includes a first stage stored in a byte-rewritable memory and a second stage stored in a block-erasable non-volatile memory (NVM). The SSD performs the data operation in the NAND array based on the physical address. The byte-rewritable memory may any byte-rewritable persistent memory. The block-erasable low latency NVM may be a flash memory that has lower latency than NAND array.

Abstract: Apparatuses, systems, and methods are disclosed for mapping-based wear leveling for non-volatile memory. An apparatus may include one or more non-volatile memory elements, and a controller. A controller may maintain a logical-to-physical mapping for converting logical addresses to physical addresses. A logical-to-physical mapping may include a translation table that associates groups of logical addresses with groups of physical addresses, and one or more mathematical mappings. A mathematical mapping for a group of logical addresses may associate individual logical addresses within the group of logical addresses with individual physical addresses within a corresponding group of physical addresses. A controller may change at least one mathematical mapping. A controller may move data based on at least one changed mapping.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to remap logical addresses to physical addresses of the set of non-volatile memory cells according to a plurality of placement mappings and to select a new placement mapping from the plurality of placement mappings according to a cost function associated with the new placement mapping.

Abstract: Systems, apparatuses, methods, and computer program products are disclosed for updating data of write-in-place storage devices. One system includes a write-in-place memory device including a redundant storage structure and a controller for the memory device. A memory device is configured to store data across a set of stripes of a redundant storage structure. A controller is configured to receive updated data for a dataset stored across a first stripe, generate a new parity for the dataset based on the updated data, overwrite the dataset across the first stripe with the updated data, and/or write the new parity to the set of stripes.

Abstract: Systems, apparatuses, methods, and computer program products are disclosed for updating data of write-in-place storage devices. One system includes a write-in-place memory device including a redundant storage structure and a controller for the memory device. A memory device is configured to store data across a set of stripes of a redundant storage structure. A controller is configured to receive updated data for a dataset stored across a first stripe, generate a new parity for the dataset based on the updated data, overwrite the dataset across the first stripe with the updated data, and/or write the new parity to the set of stripes.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for redundant array of independent disks (RAID) stripe physical placement. An apparatus includes a plurality of memory die comprising physical pages for storing data. An apparatus includes a control circuit that assigns addresses to a plurality of data stripes, wherein the control circuit assigns the addresses to the plurality of data stripes by: assigning stripe pages of a data stripe of the plurality of data stripes to different memory die of a plurality of memory die; and assigning adjacent stripe pages of the data stripe to different page numbers.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to remap logical addresses to physical addresses of the set of non-volatile memory cells according to a plurality of placement mappings and to select a new placement mapping from the plurality of placement mappings according to a cost function associated with the new placement mapping.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to group physical addresses of the set of non-volatile memory cells into groups of configurable sizes and to individually apply wear leveling schemes to non-volatile memory cells of a group.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to map the set of non-volatile memory cells into a plurality of regions, apply a first wear leveling scheme in a first region of the plurality of regions, and apply a second wear leveling scheme between the plurality of regions.