Patents by Inventor Chandarasekaran Ramamurthy

Chandarasekaran Ramamurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9734272
    Abstract: This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: August 15, 2017
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Dan Wheeler Patterson, Chandarasekaran Ramamurthy, Srivatsan Chellappa
  • Publication number: 20150363517
    Abstract: This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 17, 2015
    Applicant: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Dan Wheeler Patterson, Chandarasekaran Ramamurthy, Srivatsan Chellappa
  • Patent number: 9054688
    Abstract: This disclosure relates generally to sequential state elements (SSEs). More specifically, embodiments of flip-flops are disclosed, along with computerized methods and systems of designing the same. In one embodiment, the flip-flop includes a substrate and subcircuits that are formed on the substrate. The subcircuits provide subfunctions, wherein each of the subcircuits provides at least one of the subfunctions. More specifically, the subfunctions are provided in a sequential logical order by the subcircuits so that the flip-flop provides a flip-flop function. However, the subcircuits are interleaved out of the sequential logical order with respect to a corresponding subfunction provided by each of the subcircuits along a vector defined by the substrate. In this manner, interleaving the subcircuits along the vector of the substrate can provide separation between charge collection nodes without requiring increases in size. Thus, the flip-flop can be more compact and less expensive to manufacture.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: June 9, 2015
    Assignee: Arizona Board of Regents, a body corporate of the State of Arizona, acting for and on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Sandeep Shambhulingaiah, Sushil Kumar, Chandarasekaran Ramamurthy
  • Publication number: 20140077854
    Abstract: This disclosure relates generally to sequential state elements (SSEs). More specifically, embodiments of flip-flops are disclosed, along with computerized methods and systems of designing the same. In one embodiment, the flip-flop includes a substrate and subcircuits that are formed on the substrate. The subcircuits provide subfunctions, wherein each of the subcircuits provides at least one of the subfunctions. More specifically, the subfunctions are provided in a sequential logical order by the subcircuits so that the flip-flop provides a flip-flop function. However, the subcircuits are interleaved out of the sequential logical order with respect to a corresponding subfunction provided by each of the subcircuits along a vector defined by the substrate. In this manner, interleaving the subcircuits along the vector of the substrate can provide separation between charge collection nodes without requiring increases in size. Thus, the flip-flop can be more compact and less expensive to manufacture.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 20, 2014
    Applicant: Arizona Board of Regents, a body corporated of the State of Arizona, acting for and on behalf of Ari
    Inventors: Lawrence T. Clark, Sandeep Shambhulingaiah, Sushil Kumar, Chandarasekaran Ramamurthy