Patents by Inventor Chandra A
Chandra A has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10761976Abstract: A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. The mapping information is consistent over an on-period of a power cycle, but changes from one power cycle to another. The mapping information, such as a key value for example, may be stored in non-volatile memory such as, for example, a correlated electron random switch (CES) storage element. The mapping may be obtained by manipulating bits of the logical address to obtain the physical address.Type: GrantFiled: November 28, 2016Date of Patent: September 1, 2020Assignee: ARM LimitedInventors: Mudit Bhargava, Joel Thornton Irby, Vikas Chandra
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Patent number: 10764059Abstract: Various examples are directed to systems and methods for communications security. For example, a computing device may generate a connection between the computing device and a client device. A first application executing at the computing device may send a first application session key to the client device via the connection. The first application may perform a cryptographic operation on a first message based at least in part on the first application session key to generate a first cryptographic result and send the first cryptographic result to the client device via the connection. The first application may receive a second cryptographic result from the client device via the connection and determine that the second cryptographic result was obtained with the first application session key.Type: GrantFiled: May 31, 2016Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Brian J. Hernacki, Sumanth Naropanth, Chandra Prakash Gopalaiah
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Publication number: 20200273719Abstract: A method of attaching one or more active devices on one or more substrates to a metal carrier by “hot stamping” is disclosed. The method includes contacting the active device(s) on the substrate(s) with the metal carrier, and applying pressure to and heating the active device(s) on the substrate(s) and the metal carrier sufficiently to affix or attach the active device(s) on the substrate(s) to the metal carrier. The active device(s) may include an integrated circuit. The substrate(s) may include a metal substrate on the backside of the active device and a protective/carrier film on the frontside of the active device. The protective/carrier film may be or include an organic polymer. The metal carrier may be or include a metal foil. Various examples of the method further include thinning the metal substrate, dicing the active device(s) and a continuous substrate, and/or separating the active devices.Type: ApplicationFiled: February 26, 2020Publication date: August 27, 2020Applicant: Thin Film Electronics ASAInventors: Miki TRIFUNOVIC, Aditi CHANDRA, Anand DESHPANDE, Arvind KAMATH
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Publication number: 20200274766Abstract: The present technology provides a system, method and computer-readable medium for configuration pattern recognition and inference, directed to a device with an existing configuration, through an extensible policy framework. The policy framework uses a mixture of python template logic and CLI micro-templates as a mask to infer the intent behind an existing device configuration in a bottom-up learning inference process. Unique values for device/network identifiers and addresses as well as other resources are extracted and accounted for. The consistency of devices within the fabric is checked based on the specific policies built into the extensible framework definition. Any inconsistencies found are flagged for user correction or automatically remedied by a network controller. This dynamic configuration pattern recognition ability allows a fabric to grow without being destroyed and re-created, thus new devices with existing configurations may be added and automatically configured to grow a Brownfield fabric.Type: ApplicationFiled: February 25, 2019Publication date: August 27, 2020Inventors: Jason David Notari, Manish Chandra Agrawal, Liqin Dong, Lukas Krattiger, Patnala Debashis Rao
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Publication number: 20200272437Abstract: Provided is a method and system for building a compliance software service using reusable and configurable components. In one example, the method may include receiving a request to build a software in association with an identified jurisdiction from among a plurality of jurisdictions, retrieving a plurality of configurable software components which comprise built-in functionality that is generic across the plurality of jurisdictions, dynamically configuring non-generic functionality for the identified jurisdiction within the plurality of configurable software components based on inputs received from a user, and creating a software program for the identified jurisdiction based on the dynamically configured software components and storing a file including the created software program in a storage device.Type: ApplicationFiled: May 11, 2020Publication date: August 27, 2020Inventors: Karthik Thiru, Ravi Natarajan, Prateek Tripathi, Soumya Ranjan Das, ANKIT JAIN, Kishan Rao Ramesh Yaradi, Vijayalakshmi Mohandoss, Avinash Bhaskar, Kartik Chandra, Pavithra Thiagarajan, Yatendra Kumar Tiwari
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Publication number: 20200272539Abstract: Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures.Type: ApplicationFiled: May 14, 2020Publication date: August 27, 2020Applicant: Micron Technology, Inc.Inventor: Chandra C. Varanasi
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Patent number: 10756093Abstract: Some embodiments include a method of forming an integrated assembly. Conductive blocks are formed over a construction. Each of the conductive blocks is over a set which includes a pair of storage-element-contact-regions and a digit-line-contact-region. Each of the conductive blocks is entirely laterally surrounded by first insulative material. Central regions of the conductive blocks are removed to split each of the conductive blocks into a first conductive portion over one of the storage-element-contact-regions and a second conductive portion over another of the storage-element-contact-regions. Second insulative material is formed between the first and second conductive portions. Digit-lines are coupled with the digit-line-contact-regions, and storage-elements are coupled with the storage-element-contact-regions.Type: GrantFiled: March 6, 2019Date of Patent: August 25, 2020Assignee: Micron Technology, Inc.Inventors: Deepak Chandra Pandey, Kamal M. Karda, Haitao Liu
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Patent number: 10756217Abstract: Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.Type: GrantFiled: September 17, 2018Date of Patent: August 25, 2020Assignee: Micron Technology, Inc.Inventors: Haitao Liu, Yunfei Gao, Kamal M. Karda, Deepak Chandra Pandey, Sanh D. Tang, Litao Yang
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Patent number: 10752618Abstract: The present invention provides improved, commercially viable and consistently reproducible processes for the preparation of pure and stable crystalline Raltegravir potassium Form 3 and pharmaceutical composition thereof.Type: GrantFiled: September 13, 2017Date of Patent: August 25, 2020Assignee: LUPIN LIMITEDInventors: Purna Chandra Ray, Samir Shanteshwar Shabade, Surinder Kumar Arora, D. Rajput Lalitkumar, B. Shivdavkar Radhakrishna, G. Varade Shantanu, D. Ausekar Govind, Girij Pal Singh, Shreyas Pandurang Deshmukh, Gaurav Amrut Patil
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Patent number: 10754704Abstract: Disclosed embodiments provide techniques for load balancing of computer jobs in a distributed computer network. A health score is determined for each node of the pool of nodes, which can include native applications, virtual machines, and/or containers. A future resource availability score is determined for each node of the pool of nodes corresponding with a predetermined future time. A schedule eligibility score is computed for each node based on the health score and future resource availability score. A new job is assigned to the node with the optimal schedule eligibility score. In this way, rather than only considering the current workload conditions of the node, a future resource availability score is computed for each node, and this score is used as a factor in the assigning of jobs to the node. This provides an opportunity for improved resource utilization and improved overall system reliability.Type: GrantFiled: July 11, 2018Date of Patent: August 25, 2020Assignee: International Business Machines CorporationInventors: Suryanarayana Rao, Ramesh Chandra Pathak, Sashi Bhusan Jena, Bibhuti B. Mohanty
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Patent number: 10754651Abstract: Embodiments are generally directed to register bank conflict reduction for multi-threaded processor execution units. An embodiment of an apparatus includes a processor including one or more execution units (EUs), at least a first execution unit (EU) to process a plurality of threads, the first EU including a register file including multiple register banks with each register bank including multiple registers, and one or more read multiplexers to read registers from the register file, wherein attempting to read more than one register from a single register bank of the register file in a same clock cycle generates a register bank conflict. Registers for each thread for the first EU are distributed across the registers banks within the register file such that a first register for a first thread of the plurality of threads and a following second register for the first thread are located in different register banks within the register file.Type: GrantFiled: June 29, 2018Date of Patent: August 25, 2020Assignee: INTEL CORPORATIONInventors: Chandra Gurram, Subramaniam Maiyuran, Buqi Cheng, Ashutosh Garg, Guei-Yuan Lueh, Wei-Yu Chen
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Patent number: 10751928Abstract: A system and method are provided for conditioning paint roller cover fabric inline in a continuous paint roller manufacturing process. The system and method provide an inline fabric conditioning unit upstream of the point in the process that the paint roller fabric cover strip is wrapped about the outer side of the outer strip, the fabric conditioning unit including a fabric conditioning device that conditions the paint roller fabric cover strip as it is being fed towards the outer side of the outer strip. The fabric conditioning unit may be used to perforate the fabric, to remove loose fibers from the fabric side of the paint roller fabric cover, to buff the paint roller fabric, and to orient the paint roller cover fibers.Type: GrantFiled: February 13, 2020Date of Patent: August 25, 2020Inventors: Chandra Sekar, Santosh Sekar
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Patent number: 10754401Abstract: In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies, ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. The controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.Type: GrantFiled: May 20, 2019Date of Patent: August 25, 2020Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventors: Srirama Chandra, Robert Bartel
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Patent number: 10757708Abstract: In embodiments of battery-backed RAM for wearable devices, a mobile device, such as a mobile phone, tablet computer, or other portable device is implemented for wireless connection with a wearable device, such as a smartwatch, exercise tracking device, glasses device, or other wearable device that implements computing technology. The wearable device can store data in battery-backed RAM in the wearable device, and the mobile device can back-up the data with battery-backed RAM in the mobile device when the data is received from the wearable device. A wireless connection can be established for wireless data communication between the wearable device and the mobile device. A data manager can detect a low battery condition of the wearable device, which initiates the data being transferred from the wearable device to the mobile device via the wireless connection.Type: GrantFiled: May 11, 2018Date of Patent: August 25, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Anirudh Badam, Ranveer Chandra, Edmund Bernard Nightingale, Jian Huang
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Patent number: 10757521Abstract: A stereo parameter conditioner performs a conditioning operation on a first value of a stereo parameter and a second value of the stereo parameter to generate a conditioned value of the stereo parameter. The first value is associated with a first frequency range, and the second value is associated with a second frequency range. The conditioned value is associated with a particular frequency range that is a subset of the first frequency range or a subset of the second frequency range.Type: GrantFiled: June 11, 2019Date of Patent: August 25, 2020Assignee: QUALCOMM IncorporatedInventors: Venkata Subrahmanyam Chandra Sekhar Chebiyyam, Venkatraman Atti
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Publication number: 20200266705Abstract: A Voltage Regulator Module (VRM) includes a first voltage rail circuit board oriented in a first plane having formed therein a first plurality of conductors and configured to produce a first rail voltage, a second voltage rail circuit board oriented in a second plane that is substantially parallel to the first plane having formed therein a second plurality of conductors and configured to produce a second rail voltage. The VRM also includes a first capacitor circuit board oriented in a third plane that is (substantially perpendicular to the first plane and a second capacitor circuit board oriented in a fourth plane that is substantially parallel to the third plane. The VRM includes a plurality of conductors intercoupling the first voltage rail circuit board, the first capacitor circuit board, the second voltage rail circuit board, and the second capacitor circuit board.Type: ApplicationFiled: November 7, 2018Publication date: August 20, 2020Inventors: Shishuang Sun, Kevin Hurd, Satyan Chandra
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Publication number: 20200260784Abstract: The present invention provides a conductive substrate useful for Joule heating, such as in an electronic smoking article. Particularly, the invention provides a resistive heating element formed of a conductive substrate. The conductive substrate comprises an electrically conductive material and a carbonaceous additive, such as a binder material. The conductive substrate is carbonized in that it is subjected to calcining conditions to effectively reduce the carbonaceous additive to its carbon skeleton. It has been found that such carbonized substrate has surprisingly improved resistance properties in relation a substrate of the same formulation that is not carbonized. The carbonized substrate can include an aerosol precursor material. The formed resistive heating element can be included in an electronic smoking article to simultaneously provide resistive heating and aerosol formation with a single, unitary component.Type: ApplicationFiled: May 4, 2020Publication date: August 20, 2020Inventors: David William Griffith, JR., Yi-Ping Chang, Calvin W. Henderson, Ricky Lee Montgomery, Walter Charles Liebscher, II, Chandra Kumar Banerjee, Paul E. Braxton, Stephen Benson Sears, Kenneth Allen Beard, Timothy Brian Nestor, Balager Ademe, Frederic Philippe Ampolini, Dennis Lee Potter
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Publication number: 20200265436Abstract: A method and a system for processing transactions is provided. A terminal device executes a terminal action analysis on a transaction initiated at the terminal device by way of a transaction card. The terminal device compares a fraud count of the terminal device with a threshold fraud limit. If the fraud count exceeds the threshold fraud limit, the terminal device selects a first action from a set of actions for processing the transaction. When the first action is to authorize the transaction online, the terminal device transmits transaction details of the transaction to an acquirer server. The transaction details are indicative of a result of the terminal action analysis. The acquirer server generates an authorization request including a fraud indicator and updates the fraud indicator from a first value to a second value. The acquirer server communicates the authorization request, including the updated fraud indicator, to an issuer for authorization.Type: ApplicationFiled: January 24, 2020Publication date: August 20, 2020Applicant: Mastercard International IncorporatedInventors: Vikas Chandra, Balamurali Balasubramanian
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Patent number: 10749951Abstract: An aspect of the present disclosure facilitates selection of leader nodes in distributed data services. In one embodiment, a distributed data service is provided operative based on multiple nodes. Upon receiving from a user a selection of a set of nodes that are preferred as leader nodes, a node contained in the set of nodes is set as a leader node in the distributed data service in view of the selection by the user. Accordingly, a user is provided control over the selection of leader nodes in the distributed data service.Type: GrantFiled: April 30, 2019Date of Patent: August 18, 2020Assignee: YugaByte IncInventors: Bogdan-Alexandru Matican, Rahul Desirazu, Karthik Ranganathan, Kannan Muthukkaruppan, Bharat Chandra Baddepudi, Ramkumar Vaidyanathan Sri, Choudhury Sidharth
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Patent number: 10748900Abstract: Embodiments of the invention include a semiconductor structure and a method of making such a structure. In one embodiment, the semiconductor structure comprises a first fin and a second fin formed over a substrate. The first fin may comprise a first semiconductor material and the second fin may comprise a second semiconductor material. In an embodiment, a first cage structure is formed adjacent to the first fin, and a second cage structure is formed adjacent to the second fin. Additionally, embodiments may include a first gate electrode formed over the first fin, where the first cage structure directly contacts the first gate electrode, and a second gate electrode formed over the second fin, where the second cage structure directly contacts the second gate electrode.Type: GrantFiled: December 22, 2015Date of Patent: August 18, 2020Assignee: Intel CorporationInventors: Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Chandra S. Mohapatra, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani