Abstract: A method for establishing protected connections includes determining a primary path to a first node through a first layer of a multi-layer network. The primary path comprises a plurality of first layer links. At least one link of the plurality of first layer links comprises at least one second layer link at a second layer. The method also includes determining a secondary path to the first node through the first layer. Upon detecting a first link of the plurality of first layer links is protected against link failure by the at least one second layer link the secondary path comprises the first link of the first layer. Additionally, upon detecting a second link of the plurality of first layer links is not protected against link failure by the at least one second layer link, the secondary path comprises a third link of the first layer.

Abstract: A system and method for a generalized packet header suppression mechanism is described. This mechanism is implemented via a descriptor table. An exact copy of the descriptor table is stored in both the sender and receiver of packets via a communication medium. Entries in the descriptor table provide the information necessary to both suppress and expand the headers of well-known packets. The sender of the packet uses the descriptor table to suppress the packet header prior to transmitting the packet over the communication medium. When the packet reaches the receiver, the receiver uses the descriptor table to expand or reconstruct the packet header. This procedure results in less bandwidth required to transmit well-known messages because known header data is not transmitted via the medium, thereby not wasting bandwidth. The suppression mechanism allows the complete suppression of the header of a packet (as opposed to the traditional payload suppression) by a shorter message descriptor.

Abstract: A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.

Abstract: Thermoplastic compositions and methods of making the compositions are disclosed. The thermoplastic compositions include poly(arylene ether), a poly(alkenyl aromatic), an organophosphate ester flame retardant, a functionalized polysiloxane, and an organic acid. The thermoplastic compositions produce surprisingly low smoke density when burned, and they are useful for the fabrication of articles for the transportation and building and construction industries.

Abstract: The present invention relates to immunoconjugates for use in neutron capture therapy, in particular Boron neutron capture therapy, for killing target cells such as tumours. The immunoconjugate of the invention comprises a monoclonal antibody having an affinity of at least 1011 l/mol and a cross-reactivity of less than 10%, and a neutron capture agent. More preferably, the affinity of the monoclonal antibody is at least 1012 l/mol.

Abstract: The invention relates to a layered structure comprising a first intermediate layer, said first intermediate layer comprising at least one element of group IVB, group VB or group VIB; a second intermediate layer deposited on top of said first intermediate layer, said second intermediate layer comprising a diamond-like nanocomposite composition; a diamond-like carbon layer deposited on top of said second intermediate layer. The invention further relates to the use of a substrate coated with such a layered structure for high shear and/or high impact applications and to a method to cover a substrate with such a layered structure.

Abstract: A method, system, and program key-controlled object-based memory protection are provided. A processing unit includes an authority check for controlling access by the processing unit to pages of memory according to whether a hardware protection key set currently loaded in an authority mask register allows access to the pages. In particular, each page of memory is assigned a page key number that indexes into the hardware protection key set. The currently loaded hardware protection key set specifies those page key numbers that are currently accessible to the processing unit for the execution context. Each hardware key within the hardware protection key set may be associated with a particular data object or group of data objects. Thus, effectively, the currently loaded hardware protection key set identifies which data objects or groups of data objects are currently accessible.

Abstract: A method for minimizing a range of at least one operating mode of a powered system provided in a mission plan, the method including determining an amount of time a powered system enters a range of at least one operating mode at least one of prior to beginning a mission and while performing the mission and notifying an operator of the powered system and/or a remote monitoring facility of the amount of time the powered system enters the range of the at least one operating mode while performing the mission and/or will enter the range of the at least one operating mode prior to beginning the mission.

Abstract: The present invention provides a method and system for providing a legal sequential combination of commands for verification testing of a computer system. Executable test commands are used to form sequentially ordered “buckets” of commands, wherein each bucket command sequence is legal under at least one rule. The buckets may be arranged in any sequential order, wherein a composite command sequence of the combined commands remains legal under the at least one rule. A further advantage of the invention is that wait/noop commands may be inserted within and between the buckets, extending the testing capabilities of the present invention into corner cases.

Abstract: A method for reducing the number of channels that are scanned during a handoff situation for a wireless endpoint station in a wireless local area network (WLAN), such as an IEEE 802.11 network, by tracking past user movements within the WLAN. A suitable sequence of channels to be scanned is generated so that reduce the number of handoffs are reduced and the average time during a handoff is reduced. To reduce handoffs and handoff latencies, the principle of locality (user movement patterns tend to be repetitive) is used. By tracking the past handoffs, future handoffs are predicted.

Abstract: A process is described for wavelength conversion of LED light using phosphors. LED dies are tested for correlated color temperature (CCT), and binned according to their color emission. The LEDs in a single bin are mounted on a single submount to form an array of LEDs. Various thin sheets of a flexible encapsulant (e.g., silicone) infused with one or more phosphors are preformed, where each sheet has different color conversion properties. An appropriate sheet is placed over an array of LED mounted on a submount, and the LEDs are energized. The resulting light is measured for CCT. If the CCT is acceptable, the phosphor sheet is permanently laminated onto the LEDs and submount. The lamination encapsulates each LED to protect the LEDs from contaminants and damage. The LEDs in the array of LEDs on the submount are separated. By selecting a different phosphor sheet for each bin of LEDs, the resulting CCT is very uniform across all bins.

Abstract: Methods and apparatus to manage power consumption in wireless devices are disclosed. A disclosed example apparatus comprises a motion detector to detect motion, and a wireless modem to perform a background scan when motion is detected.

Abstract: A non-volatile storage system in which body bias can be applied to optimize performance. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Abstract: A system and method for transmitting protected real-time content from one user to another is described. In a first aspect, a user sends a Rights Object to another user. In a second aspect, a user sends a Rights Object to another user via an intermediate server for a multiparty communication. In this second aspect, the users may be able to switch between designated Rights Objects as needed.

Abstract: In the semi-arid region, particularly in hard rock terrain, shallow aquifers are major source of potable groundwater. These aquifers are indiscriminately exploited to meet the growing demand of water for domestic, irrigation as well as industrial use. In order to achieve a sustainable development, it is essential not only to delineate the groundwater potential zone and but also suitable augmentation scheme which in turn requires delineation of feasible recharge zone. Such zones are conventionally delineated through the application of various indirect methods such as hydro-geomorphological, geological and geophysical, which many times are time consuming and uneconomical. A simple, efficient and cost-effective cross correlation based process which takes into consideration the study of aquifer response to rainfall is provided in the present invention to delineate groundwater recharge zone.

Abstract: This disclosure relates to methods and compositions for modulating disease resistance in plants and transgenic plants comprising reducing the amount of 18:1 fatty acids.

Abstract: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Abstract: A method (and system) which provides virtual machine migration with filtered network connectivity and control of network security of a virtual machine by enforcing network security and routing at a hypervisor layer at which the virtual machine partition is executed, and which is independent of guest operating systems.

Abstract: A non-volatile storage system in which a body bias is applied to compensate for performance variations which are based on the position of a selected word line which is associated with non-volatile storage elements undergoing program, read or verify operations. In one approach, the body bias increases when the selected word line is closer to a drain side of a NAND string than a source side. In another approach, the body bias varies when the selected word line is an end word line. In another approach, first or second body bias levels can be used when the selected word line is in a first or second group of word lines, respectively. The body bias reduces variations in threshold voltage levels and threshold voltage distributions which are based on the selected word line position. Gate-induced drain leakage (GIDL) is also reduced.

Abstract: A valve assembly for a clothes treating apparatus operable in a dry cleaning process and a water washing process includes a valve inlet, and first and second valve outlets coupled in flow communication with the valve inlet. The apparatus includes a cabinet, and a wash tub and a storage tank positioned within the cabinet. The valve inlet is configured to be coupled in flow communication with the wash tub. The valve assembly also includes a first valve and a second valve configured to respectively control the flow through the first valve outlet and the second valve outlet. The first valve is configured to channel liquid from the wash tub outward through the first valve outlet in the water washing process, and the second valve is configured to channel liquid from the wash tub outward through the second valve outlet in the dry cleaning process.