Abstract: A processing device in a memory sub-system configured to receive an instruction to configure an input/output (I/O) command submission queue in a warp mode; configuring, in a host memory of the host system, the I/O command submission queue comprising a linear memory buffer associated with a plurality of warp offset pointers, wherein each warp offset pointer identifies, among a plurality of sections of the I/O command submission queue, a respective section associated with a respective warp of a plurality of warps of the host system, and wherein the respective warp comprises a respective set of processing threads of the host system that synchronously execute a same sequence of executable instructions; and associate, with each section of the plurality of sections of the I/O command submission queue, a respective doorbell register for signaling a presence of one or more I/O commands in the section of the I/O command submission queue.

Abstract: A processing device in a memory sub-system configured to receive, from a host system, a sequence of input/output (I/O) commands associated with a warp of the host system, wherein the warp comprises a set of processing threads of the host system that synchronously execute a same sequence of executable instructions; receive a context attribute associated with the warp; execute the sequence of I/O commands by performing, based on the context attribute, a plurality of memory access operations with respect to the memory device.

Abstract: A processing device in a memory sub-system configured to receive, from a host system, a sequence of input/output (I/O) commands associated with a warp of the host system, wherein the warp comprises a set of processing threads of the host system that synchronously execute a same sequence of executable instructions; execute the sequence of I/O commands by performing a plurality of memory access operations with respect to the memory device; and responsive to executing the sequence of I/O commands, report a completion status to the host system.

Abstract: A processing device in a memory sub-system detects an occurrence of a scan ahead trigger event in a memory sub-system, initiates a scan ahead operation of a plurality of command submission queues in a host system coupled to the memory sub-system to read a plurality of pending command submission queue entries from the plurality of command submission queues, and stores respective indications of the plurality of pending command submission queue entries in a cache memory of the memory sub-system.

Abstract: A processing device in a memory sub-system detects an occurrence of a scan ahead trigger event in a memory sub-system, initiates a scan ahead operation of a plurality of command submission queues in a host system coupled to the memory sub-system to read a plurality of pending command submission queue entries from the plurality of command submission queues, and stores respective indications of the plurality of pending command submission queue entries in a cache memory of the memory sub-system.

Abstract: A system includes a memory device; and a processing device, operatively coupled with the memory device, to perform operations including: receiving, from a host system, a first write request, wherein the first write request includes a first data item and a first placement identifier; identifying, based on the first placement identifier, a region of the memory device, wherein the region of the memory device is configured to store a lowest number of bits per cell supported by the memory device; writing the first data item in a first set of blocks in the region of the memory device, wherein the first set of blocks is mapped to a first logical block address corresponding to the first data item; receiving, from the host system, a deallocation command, wherein the deallocation command specifies the first logical block address corresponding to the first data item being invalid; identifying, based on the first logical block address, the first set of blocks in the region of the memory device; erasing the first set of b

Abstract: A system includes a memory device and a processing device coupled to the memory device, the processing device is to perform operations including: receiving, from a host system, a first write request, wherein the first write request includes a first data item and a first namespace; identifying, based on the first namespace, a region of the memory device, wherein the region is configured to store a lowest number of bits per cell supported by the memory device; and writing the first data item to the region of the memory device.

Abstract: A system includes a memory device and a processing device coupled to the memory device, the processing device is to perform operations including: receiving, from a host system, a first write request, wherein the first write request includes a first data item and a first placement identifier; identifying, based on the first placement identifier, a region of the memory device, wherein the region is configured to store a lowest number of bits per cell supported by the memory device; and writing the first data item to the region of the memory device.

Abstract: A processing device in a memory sub-system detects an occurrence of a scan ahead trigger event in a memory sub-system, initiates a scan ahead operation of a plurality of command submission queues in a host system coupled to the memory sub-system to read a plurality of pending command submission queue entries from the plurality of command submission queues, and stores respective indications of the plurality of pending command submission queue entries in a cache memory of the memory sub-system.

Abstract: A just-in-time (JIT) scheduling method includes the operations of: receiving a request to perform a memory operation using a hardware resource associated with a memory device; determining a type of the memory operation; identifying a traffic class corresponding to the memory operation; determining, based on the traffic class and the type of the memory operation, whether the memory operation is to be processed during a current scheduling time frame; and responsive to determining the memory operation is to be processed during the current scheduling time frame, submitting the memory operation to the memory device.

Abstract: The memory sub-systems of the present disclosure discloses a just-in-time (JIT) scheduling system and method. In one embodiment, a system receives a request to perform a memory operation using a hardware resource associated with a memory device. The system identifies a traffic class corresponding to the memory operation. The system determines a number of available quality of service (QoS) credits for the traffic class during a current scheduling time frame. The system determines a number of QoS credits associated with a type of the memory operation. Responsive to determining the number of QoS credits associated with the type of the memory operation is less than the number of available QoS credits, the system submits the memory operation to be processed at a memory device.

Abstract: A processing device in a memory system determines to send system state information associated with the memory device to a host system and identifies a subset of a plurality of event entries from a staging buffer based on one or more filtering factors, the plurality of event entries corresponding to events associated with the memory device. The processing device further sends the subset of the plurality of event entries as the system state information to the host system over a communication pipe having limited bandwidth.

Abstract: The memory sub-systems of the present disclosure discloses a simulator to simulate a QoS latency model for a just-in-time (JIT) scheduler. In one embodiment, a system receives a workload profile specifying a sequence of memory operations, wherein each memory operation is associated with a type of the memory operation. The system identifies a traffic class associated with each memory operation of the sequence of memory operations. The system queues each memory operation of the sequence of memory operations, based on the traffic class associated with the memory operation, in a scheduling pool of a number of scheduling pools. The system selects, based on a quality of service (QoS) policy, from the scheduling pools, one or more memory operations to be serviced within a scheduling time frame. The system determines, based on a latency profile, latency periods for each memory operation of the one or more memory operations.

Abstract: The memory sub-systems of the present disclosure discloses a just-in-time (JIT) scheduling system and method. In one embodiment, a system receives a request to perform a memory operation using a hardware resource associated with a memory device. The system identifies a traffic class corresponding to the memory operation. The system determines a number of available quality of service (QoS) credits for the traffic class during a current scheduling time frame. The system determines a number of QoS credits associated with a type of the memory operation. Responsive to determining the number of QoS credits associated with the type of the memory operation is less than the number of available QoS credits, the system submits the memory operation to be processed at a memory device.

Abstract: A processing device in a memory system determines to send system state information associated with the memory device to a host system and identifies a subset of a plurality of event entries from a staging buffer based on one or more filtering factors, the plurality of event entries corresponding to events associated with the memory device. The processing device further sends the subset of the plurality of event entries as the system state information to the host system over a communication pipe having limited bandwidth.

Abstract: A processing device in a memory system determines to send system state information associated with the memory device to a host system and identifies a subset of a plurality of event entries from a staging buffer based on one or more filtering factors, the plurality of event entries corresponding to events associated with the memory device. The processing device further sends the subset of the plurality of event entries as the system state information to the host system over a communication pipe having limited bandwidth.

Abstract: A processing device in a memory system receives, from a host system, a request for a debug slave address associated with a system management bus port of a memory sub-system and sends a response comprising the debug slave address to the host system. The processing device receives, from the host system, a request to enable the system management bus port to receive a request for debug information directed to the debug slave address, receives, from the host system, the request for debug information directed to the debug slave address, and sends the debug information to the host system over a system management bus coupled to the system management bus port of the memory sub-system.

Abstract: A processing device in a memory system receives, from a host system, a request for a debug slave address associated with a system management bus port of a memory sub-system and sends a response comprising the debug slave address to the host system. The processing device receives, from the host system, a request to enable the system management bus port to receive a request for debug information directed to the debug slave address, receives, from the host system, the request for debug information directed to the debug slave address, and sends the debug information to the host system over a system management bus coupled to the system management bus port of the memory sub-system.

Abstract: A processing device in a memory system receives a privilege key from a host system, the privilege key having an associated level of access to debug information associated with the memory device and determines the level of access associated with the privilege key. The processing device receives, from the host system, a request for debug information directed to a debug slave address associated with a system management bus port of a memory sub-system, identifies the debug information corresponding to the level of access associated with the privilege key, and sends the debug information to the host system over a system management bus coupled to the system management bus port of the memory sub-system.

Abstract: A processing device in a memory system determines to send system state information associated with the memory device to a host system and identifies a subset of a plurality of event entries from a staging buffer based on one or more filtering factors, the plurality of event entries corresponding to events associated with the memory device. The processing device further sends the subset of the plurality of event entries as the system state information to the host system over a communication pipe having limited bandwidth.