Abstract: A processing device determines a duration for executing a portion of an erase operation based on a plurality of execution times of erase operations performed on a memory device. The processing device executes the portion of the erase operation. Responsive to detecting expiration of the duration for executing the erase operation, the processing logic executes an erase suspend operation to suspend the erase operation. Responsive to detecting completion of the erase suspend operation, the processing logic executes one or more commands. The processing device further executes an erase resume operation to resume the erase operation on the memory device.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command; responsive to detecting that the memory access command satisfies a trigger condition, recording, in a set of registers, data associated with a plurality of events performed by processing the memory access command; and responsive to detecting that the set of registers comprises the data, disabling write operations on the set of registers.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command specifying a logical address; determining a physical address associated with the logical address; determining a portion of the memory device that is referenced by the physical address; determine an endurance factor associated with the portion; and increasing, by a value derived from the endurance factor, a media management metric associated with a management unit of the memory device, wherein the management unit is referenced by the physical address.

Abstract: A system includes a memory device; a volatile memory comprising buffers; and a processing device to perform operations comprising: accessing a read command having a first command tag, the first command tag comprising a first logical transfer unit (LTU) value and a first buffer address for a first buffer, the first LTU value being mapped from a zone of a plurality of sequential logical block address (LBA) values to a first physical address, of the memory device, at which is stored first data; and generating a set of command tags that are to cause second data to be retrieved from the memory device and stored in a set of the buffers, wherein the set of command tags comprises at least a second command tag associated with a second physical address that sequentially follows the first physical address.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command specifying a logical address; determining a physical address associated with the logical address; determining a portion of the memory device that is referenced by the physical address; determine an endurance factor associated with the portion; and increasing, by a value derived from the endurance factor, a media management metric associated with a management unit of the memory device, wherein the management unit is referenced by the physical address.

Abstract: A system includes a memory device; a volatile memory comprising buffers; and a processing device to perform operations comprising: accessing a read command having a first command tag, the first command tag comprising a first logical transfer unit (LTU) value and a first buffer address for a first buffer, the first LTU value being mapped from a zone of a plurality of sequential logical block address (LBA) values to a first physical address, of the memory device, at which is stored first data; and generating a set of command tags that are to cause second data to be retrieved from the memory device and stored in a set of the buffers, wherein the set of command tags comprises at least a second command tag associated with a second physical address that sequentially follows the first physical address.

Abstract: A system includes having buffers and a processing device that receives a read request with a logical block address (LBA) value for a memory device, creates a logical transfer unit (LTU) value, to include the LBA value, that is mapped to a first physical address of the memory device, and generates command tags that are to direct the processing device to retrieve data from the memory device and store the data in buffers. The command tags include a first command tag associated with the first physical address and a second command tag associated with a second physical address that sequentially follows the first physical address. The processor further creates an entry in the read cache table for the buffers. The entry can include a starting LBA value set to the first LBA value and the read offset value corresponding to the amount of data.

Abstract: A processing device determines a duration for executing a portion of an erase operation based on a plurality of execution times of erase operations performed on a memory device. The processing device executes the portion of the erase operation. Responsive to detecting expiration of the duration for executing the erase operation, the processing logic executes an erase suspend operation to suspend the erase operation. Responsive to detecting completion of the erase suspend operation, the processing logic executes one or more commands. The processing device further executes an erase resume operation to resume the erase operation on the memory device.

Abstract: A processing device in a memory system receives a privilege key from a host system, the privilege key having an associated level of access to debug information associated with the memory device and determines the level of access associated with the privilege key. The processing device receives, from the host system, a request for debug information directed to a debug slave address associated with a system management bus port of a memory sub-system, identifies the debug information corresponding to the level of access associated with the privilege key, and sends the debug information to the host system over a system management bus coupled to the system management bus port of the memory sub-system.

Abstract: A processing device receives a request to perform an erase operation on a memory device. The processing device executes a portion of the erase operation during a first time period. The processing device further executes an erase suspend operation to suspend the erase operation during the first time period. Responsive to detecting a completion of the erase suspend operation, the processing device receives one or more commands directed to the memory device. The processing device also executes the one or more commands during a second time period. Responsive to the expiration of the second time period, the processing device executes an erase resume operation to resume the erase operation on the memory device.

Abstract: A system includes a volatile memory having buffers and a processing device. A command generation processor receives, from a host, a read request with a logical block address (LBA) and creates a first logical transfer unit (LTU), including the first LBA, that is to be mapped to a physical address. The command generation processor reads a flag to determine that the first LTU is associated with a zone of LBA address space, the zone including sequential LBAs that are sequentially mapped to sequential physical addresses. The command generation processor generates command tags that are to direct the processing device to retrieve the data from the memory device and store the data in a set of the buffers, where the command tags include a first command tag associated with the physical address and a second command tag associated with a second physical address that sequentially follows the physical address.

Abstract: A system includes having buffers and a processing device that receives a read request with a logical block address (LBA) value for a memory device, creates a logical transfer unit (LTU) value, to include the LBA value, that is mapped to a first physical address of the memory device, and generates command tags that are to direct the processing device to retrieve data from the memory device and store the data in buffers. The command tags include a first command tag associated with the first physical address and a second command tag associated with a second physical address that sequentially follows the first physical address. The processor further creates an entry in the read cache table for the buffers. The entry can include a starting LBA value set to the first LBA value and the read offset value corresponding to the amount of data.

Abstract: A system includes a volatile memory having buffers and a processing device. A command generation processor receives, from a host, a read request with a logical block address (LBA) and creates a first logical transfer unit (LTU), including the first LBA, that is to be mapped to a physical address. The command generation processor reads a flag to determine that the first LTU is associated with a zone of LBA address space, the zone including sequential LBAs that are sequentially mapped to sequential physical addresses. The command generation processor generates command tags that are to direct the processing device to retrieve the data from the memory device and store the data in a set of the buffers, where the command tags include a first command tag associated with the physical address and a second command tag associated with a second physical address that sequentially follows the physical address.

Abstract: A processing device receives a request to perform an erase operation on a memory device. The processing device executes a portion of the erase operation during a first time period. The processing device further executes an erase suspend operation to suspend the erase operation during the first time period. Responsive to detecting a completion of the erase suspend operation, the processing device receives one or more commands directed to the memory device. The processing device also executes the one or more commands during a second time period. Responsive to the expiration of the second time period, the processing device executes an erase resume operation to resume the erase operation on the memory device.

Abstract: Lifetime extension of a non-volatile semiconductor memory (NVSM) for a data storage device (DSD) includes determining a write amplification factor based on an amount of data previously written to the NVSM and at least one of an amount of data previously requested to be written to the DSD, and an amount of data previously requested to be written to the NVSM. At least a portion of the amount of data to be written to the NVSM is directed or redirected to the disk based on the determined write amplification factor.

Abstract: A device comprises a first storage media and a controller. The controller configured to generate a first operational metric using a first set of operational data at a first frequency and a second operational metric a second set of operational data at a second frequency different than the first frequency; receive a write command to write data to the first storage media; and divert the write command to write data to a second storage media instead of the first storage media when at least one of the first operational metric and the second operational metric indicates that writing data to the first storage media may be harmful to the magnetic rotating disk or result in data loss.

Abstract: Lifetime extension of a non-volatile semiconductor memory (NVSM) for a data storage device (DSD) includes determining a write amplification factor based on an amount of data previously written to the NVSM and at least one of an amount of data previously requested to be written to the DSD, and an amount of data previously requested to be written to the NVSM. At least a portion of the amount of data to be written to the NVSM is directed or redirected to the disk based on the determined write amplification factor.

Abstract: A data storage device can include a magnetic rotating disk, a solid state memory, and a controller. The controller is configured to generate a first operational metric which is updated at a first frequency and a second operational metric which is updated at a second frequency different than the first frequency, receive a write command to write data to the magnetic rotating disk, and divert the write command to write data to the solid state memory instead of the magnetic rotating disk when at least one of the first operational metric and the second operational metric indicates that writing data to the magnetic rotating disk may be harmful to the magnetic rotating disk or result in data loss.

Abstract: Embodiments of solid-state storage system are provided herein which reduce processing delays for performance-sensitive commands. These performance-sensitive commands are typically read-write commands which can be transferred to the storage media by a high performance path to optimize responsiveness to the host. This high performance path can be enabled and disabled to prevent conflicts with commands processed via a low performance path.

Abstract: A disk drive is disclosed that utilizes multi-tiered solid state memory for caching data received from a host. Data can be stored in a memory tier that can provide the required performance at a low cost. For example, multi-level cell (MLC) memory can be used to store data that is frequently read but infrequently written. As another example, single-level cell (SLC) memory can be used to store data that is frequently written. Improved performance, reduced costs, and improved power consumption can thereby be attained.