Abstract: An efficient branch prediction structure is described that bifurcates a branch prediction structure into at least two portions where information stored in the second portion is aliased amongst multiple entries of the first portion. In this way, overall storage (and layout area) can be reduced and scaling with a branch prediction structure that includes a (2N)K×1 branch direction entries and a (N/2)K×1 branch prediction qualifier entries is less dramatic than conventional techniques. An efficient branch prediction structure includes entries for branch direction indications and entries for branch prediction qualifier indications. The branch direction indication entries are more numerous than the branch prediction qualifier entries.

Abstract: The present application describes a method and a processor for handling register dependency conflicts between lesser and greater width instructions, colloquially referred to as “evil twins.” If there is a register dependency between a greater width producer instruction and a lesser width consumer instruction, a greater width source register is substituted for the source register specified by the lesser width producer. If there is a register dependency between a lesser width producer instruction and a greater width producer instruction, the greater width consumer instruction is replaced by multiple helper instructions. One or more of the helper instructions merge lesser width registers aliased onto the source registers specified by the greater width consumer instruction, into temporary registers. Another helper instruction executes the greater width consumer instruction using the temporary registers instead of the original source registers.

Abstract: The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply, integer-divide, move on integer registers, graphics, floating point calculations or the like) are expanded into helper instructions before execution (e.g., in the integer, floating point, graphics and memory units or the like). Such instructions are treated as complex instructions. The functionality of a complex instruction is shared among multiple helpers so that by executing the helpers representing the complex instruction, the functionality of complex instruction is achieved. The expansion of complex instructions into helper instructions reduces the amount of hardware and complexity involved in supporting these individual complex instructions in various units in the processor.

Abstract: A method and apparatus for handling window management instructions without post serialization in an out-of-order multi-issue processor includes an instruction decode unit arranged to decode the window management instruction. A plurality of register windows are indexed by a current window pointer, and a working copy of the current window pointer is stored in a register in the instruction decode unit. The instruction decode unit uses the working copy of the current window pointer to handle the window management instruction.

Abstract: A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.

Abstract: A method and apparatus to determine readiness of a complex instruction for retirement includes decoding a complex instruction into a plurality of helper instructions; executing the plurality of helper instructions using an execution unit; indicating the plurality of helper instructions that are alive using a live instruction register; and maintaining a complex instruction identification for the complex instruction using a complex instruction identification register.

Abstract: A technique for flattening architectural register windows into flattened space depending on a current window pointer to a register window is provided. The technique involves converting an n-bit value of a particular register in a register window to an x-bit value dependent on the current window pointer, where x is greater than n, and where the x-bit value is used for register dependency checking among a plurality of instructions.

Abstract: A technique for handling a condition code modifying instruction in an out-of-order multi-stranded processor involves providing a condition code architectural register file for each strand, providing a condition code working register file, and assigning condition code architectural register file identification information (CARF_ID) and condition code working register file identification information (CWRF_ID) to the condition code modifying instruction. CARF_ID is used to index a location in a condition code rename table to which the CWRF_ID is stored. Thereafter, upon an exception-free execution of the condition code modifying instruction, a result of the execution is copied from the condition code working register file to the condition code architectural register file dependent on CARF_ID, CWRF_ID, register type information, and strand identification information.

Abstract: A method and apparatus determines whether there is an invalid address translation entry in a first translation look-aside buffer. If there is an invalid address translation entry in the first translation look-aside buffer, an invalid address translation entry in the first translation look-aside buffer is replaced. If there is no invalid address translation entry in the first translation look-aside buffer, a method and apparatus determines whether there is an invalid address translation entry in a second translation look-aside buffer. If there is an invalid address translation entry in the second translation look-aside buffer, an invalid address translation entry in the second translation look-aside buffer is replaced.

Abstract: A method for limiting a number of register file read ports used to process a store instruction includes decoding the store instruction, where the decoding generates a decoded store instruction, identifying a store data register and source operand registers included in the decoded store instruction, and appending a set of attribute fields to the decoded store instruction. Further, dependent on a value of at least one of the attribute fields, source values corresponding to the source operand registers are read using the register file read ports at a time that the store instruction is issued, and a store data value corresponding to the store data register is read using one of the register file read ports at a time that the store instruction is committed.

Abstract: A method for handling a control transfer instruction couple includes fetching a plurality of instructions. The plurality of instructions include a control transfer instruction couple (or CTI couple), which includes a first branch instruction and a second branch instruction, leading instructions that precede the first branch instruction, trailing instructions that follow the second branch instruction, and buffered instructions that follow the trailing instructions. The method further includes decoding the CTI couple, forwarding the leading instructions and the first branch instruction for processing, freezing the trailing instructions and the delay slot to obtain frozen instructions, buffering the buffered instructions fetched after the freezing, and initiating an instruction refetch cycle dependent on a prediction of an execution of the first branch instruction.

Abstract: A method for handling instructions that use non-windowed registers in an out-of-order microprocessor with windowed registers is provided. When an instruction with a non-windowed destination register is detected, the computed result of the instruction is stored in a temporary storage register instead of the non-windowed register designated as the instruction's destination. When the instruction is ready for retirement, the result is transferred from the temporary storage register into the non-windowed register designated as the instruction's destination. When another instruction's source register is a non-windowed register, the microprocessor determines whether the instruction should use data from the designated non-windowed register or from a temporary storage register, to prevent the other instruction from using incorrect data.

Abstract: A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.

Abstract: A method and apparatus for handling window management instructions without post serialization in an out-of-order multi-issue processor includes an instruction decode unit arranged to decode the window management instruction. A plurality of register windows are indexed by a current window pointer, and a working copy of the current window pointer is stored in a register in the instruction decode unit. The instruction decode unit uses the working copy of the current window pointer to handle the window management instruction.

Abstract: A method and apparatus for avoiding strand starvation is provided. The method and apparatus selectively switches from a first strand to a second strand dependent on a state of a computer system. The selectively switching is dependent on whether the second strand is alive and whether a value of a counter has reached a particular count.

Abstract: A method and apparatus for processing instructions involves an instruction fetch unit arranged to receive a plurality of instructions. The instruction fetch unit includes a bypass buffer arranged to receive at least a portion of a plurality of instructions, and an output multiplexer arranged to receive the at least a portion of the plurality of instructions where the output multiplexer is arranged to output an instruction selected from one of an output of the bypass buffer and the at least a portion of the plurality of instructions.

Abstract: In an embodiment, the present invention describes a method and apparatus for detecting RAW condition earlier in an instruction pipeline. The store instructions are stored in a special store bypass buffer (SBB) within an instruction decode unit (IDU). The IDU compares the instruction fields that are used for address generation of all ‘load’ instructions against ‘store’ instructions within a group of fetched instructions and ‘store’ instructions previously stored in the SBB. If a match of instruction fields is found, the IDU ‘speculates’ that the load instruction has dependency on the ‘store’ instruction. A data cache unit (DCU) validates the dependency of the load instruction ‘speculated’ by the IDU. If a false dependency is ‘speculated’ by the IDU, the DCU forces a re-fetch of the load instruction.