Abstract: A data processing system which includes a central processor unit which has an arithmetic logic unit (ALU) for performing fixed point arithmetic operations and a separate floating point unit (FPU) for performing floating point operations and which uses multi-level microcode architecture wherein each unit has its own control store (a "horizontal" store) which responds to addresses of execution control signals supplied thereto from a common control store (a "vertical" store) to produce horizontal microinstructions for performing ALU and FPU operations, respectively. Selected ones of such addresses are recognized for ALU operations by the CPU control store only, other selected ones are recognized for FPU operations by the FPU control store only, while still other selected ones are recognized for both ALU and FPU operations by both control stores so that such operations can be performed simultaneously in parallel.

Abstract: In a data processing system which uses a common bus for communication of address and data information among a plurality of system components, a bus timing technique uses a clock signal having a transfer time period which comprises a plurality of subperiods which requires address transfer to take place during a first selected group of subperiods and data to be transferred during a second selected group of subperiods with idle subperiods in between. A first control signal is generated by the data receiving or data supplying unit in order to inhibit access to the bus until such transfer is completed and a second control signal can be provided to lock-in bus access by such unit if desired for more than one transfer period. Appropriate priority is arranged for bus access among selected system components whether the common bus system has a single bus for use with a single port memory or a dual bus for use with a dual port memory.