Abstract: An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.

Abstract: Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage by a first voltage shifter and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage by a second voltage shifter.

Abstract: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Abstract: A body bias is applied to a non-volatile storage system to compensate for performance variations which are based on the position of a selected word line which is associated with non-volatile storage elements undergoing program, read or verify operations. In one approach, the body bias increases when the selected word line is closer to a drain side of a NAND string than a source side. In another approach, the body bias varies when the selected word line is an end word line. In another approach, first or second body bias levels can be used when the selected word line is in a first or second group of word lines, respectively. The body bias reduces variations in threshold voltage levels and threshold voltage distributions which are based on the selected word line position. Gate-induced drain leakage (GIDL) is also reduced.

Abstract: Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.

Abstract: A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.

Abstract: A non-volatile storage device in which power consumption is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.

Abstract: Power consumption in a non-volatile storage device is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.

Abstract: A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.

Abstract: A non-volatile storage device in which power consumption is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.

Abstract: Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.

Abstract: A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.

Abstract: Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage.

Abstract: Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage by a first voltage shifter and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage by a second voltage shifter.

Abstract: A non-volatile storage system in which a body bias is applied to compensate for performance variations which are based on the position of a selected word line which is associated with non-volatile storage elements undergoing program, read or verify operations. In one approach, the body bias increases when the selected word line is closer to a drain side of a NAND string than a source side. In another approach, the body bias varies when the selected word line is an end word line. In another approach, first or second body bias levels can be used when the selected word line is in a first or second group of word lines, respectively. The body bias reduces variations in threshold voltage levels and threshold voltage distributions which are based on the selected word line position. Gate-induced drain leakage (GIDL) is also reduced.

Abstract: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

Abstract: A body bias is applied to a non-volatile storage system to compensate for performance variations which are based on the position of a selected word line which is associated with non-volatile storage elements undergoing program, read or verify operations. In one approach, the body bias increases when the selected word line is closer to a drain side of a NAND string than a source side. In another approach, the body bias varies when the selected word line is an end word line. In another approach, first or second body bias levels can be used when the selected word line is in a first or second group of word lines, respectively. The body bias reduces variations in threshold voltage levels and threshold voltage distributions which are based on the selected word line position. Gate-induced drain leakage (GIDL) is also reduced.

Abstract: A non-volatile storage system in which a body bias is applied to a non-volatile storage system to compensate for temperature-dependent variations in threshold voltage, sub-threshold slope, depletion layer width and/or 1/f noise. A desired bias level is set based on a temperature-dependent reference signal. In one approach, a level of the biasing can decrease as temperature increases. The body bias can be applied by applying a voltage to a p-well and n-well of a substrate, applying a voltage to the p-well while grounding the n-well, or grounding the body and applying a voltage to the source and/or drain of a set of non-volatile storage elements. Further, temperature-independent and/or temperature-dependent voltages can be applied to selected and unselected word lines in the non-volatile storage system during program, read or verify operations. The temperature-dependent voltages can vary based on different temperature coefficients.

Abstract: A body bias is applied to a non-volatile storage system to compensate for temperature-dependent variations in threshold voltage, sub-threshold slope, depletion layer width and/or 1/f noise. A desired bias level is set based on a temperature-dependent reference signal. In one approach, a level of the biasing can decrease as temperature increases. The body bias can be applied by applying a voltage to a p-well and n-well of a substrate, applying a voltage to the p-well while grounding the n-well, or grounding the body and applying a voltage to the source and/or drain of a set of non-volatile storage elements. Further, temperature-independent and/or temperature-dependent voltages can be applied to selected and unselected word lines in the non-volatile storage system during program, read or verify operations. The temperature-dependent voltages can vary based on different temperature coefficients.

Abstract: A non-volatile storage system in which body bias can be applied to optimize performance. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.