Abstract: A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a first on impedance or a second on impedance to the resistive memory element in response to a control signal.

Abstract: A paint roller manufacturing system includes a cover dispenser for continuously dispensing a windable width of paint roller cover fabric, a fabric supporting and advancing device for supporting the fabric and maintaining a width-wise dimension of the paint roller cover fabric as the fabric advances, a fabric coating applicator for applying a coating to the back side of the paint roller cover fabric while the fabric supporting and advancing device maintains the fabric in a width-wise dimension, and a compressing roller positioned downstream of the fabric coating applicator and configured to apply a compressive force on the coating after it has been applied to the back side of the paint roller cover fabric and while the fabric is supported by the fabric supporting and advancing device. In two-strip embodiments, first and second strip dispensers continuously dispense a first and second windable width of strip material.

Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.

Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.

Abstract: A method for operating an automated food making apparatus having a motor, actuator arm, and an apparatus. The apparatus may be a paddle with flexible fins. The method rotates the paddle with a pin-shaft mechanism to dispense an ingredient placed in a canister, controls the motor automatically based on weight sensor readings, and locates a position of the actuator arm with position sensors. The same motor dispenses ingredients from a plurality of canisters. The method may have a plurality of paddle rotation and weight measurement steps until a target weight is reached. The plurality of paddle rotation steps may be unidirectional or bidirectional paddle rotation. The paddle may be rotated according to one or more paddle rotation algorithms, an error recovery algorithm, or different algorithms based on the amounts of ingredients remaining in the canister. The paddle may be rocked until the target weight is achieved.

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.

Abstract: A system for integrated performance measurement environment comprises a plurality of distributed file systems; a database, wherein the database further comprises a layout details table, a layout definition table, and at least one raw data master file; at least one network; an extract-transform-load module in a memory; and a business logic module in the memory, wherein the business logic module further comprises metrics catalog and business intelligent plug-in blocks; and a collaboration module in the memory; and methods performing the same including extracting, transforming, and loading data into the system, retrieving data in accordance with rules in metrics catalog and business intelligent plug-in blocks, drilling down the metrics catalog and business intelligent plug-in blocks, and collaborating over the system.

Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.

Abstract: A paint roller manufacturing system includes a cover dispenser for continuously dispensing a windable width of paint roller cover fabric, a fabric supporting and advancing device for supporting the fabric and maintaining a width-wise dimension of the paint roller cover fabric as the fabric advances, a fabric coating applicator for applying a coating to the back side of the paint roller cover fabric while the fabric supporting and advancing device maintains the fabric in a width-wise dimension, and a compressing roller positioned downstream of the fabric coating applicator and configured to apply a compressive force on the coating after it has been applied to the back side of the paint roller cover fabric and while the fabric is supported by the fabric supporting and advancing device. In two-strip embodiments, first and second strip dispensers continuously dispense a first and second windable width of strip material.

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.

Abstract: A system for integrated performance measurement environment comprises a plurality of distributed file systems; a database, wherein the database further comprises a layout details table, a layout definition table, and at least one raw data master file; at least one network; an extract-transform-load module in a memory; and a business logic module in the memory, wherein the business logic module further comprises metrics catalog and business intelligent plug-in blocks; and a collaboration module in the memory; and methods performing the same including extracting, transforming, and loading data into the system, retrieving data in accordance with rules in metrics catalog and business intelligent plug-in blocks, drilling down the metrics catalog and business intelligent plug-in blocks, and collaborating over the system.

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

Abstract: Described are methods of making a paint roller using thermoplastic strip material, adhesive and a composite cover material. The materials can be assembled in a continuous manufacturing process by helically winding a strip comprising polypropylene around a mandrel so as to form a helically wound strip, advancing the wound strip along the mandrel, applying a molten layer of adhesive comprising polypropylene onto the outer surface of the wound strip, wrapping a strip of composite cover material about the wound strip and over the layer of adhesive, and allowing the adhesive to cool, thereby laminating the composite cover material with the outer surface of the wound strip.

Abstract: A proteoliposome, which is obtained by removing a surfactant from a mixed solution including lipid, membrane proteins and the surfactant, wherein the content of the surfactant in the mixed solution is equal to or more than 1.5 times of the sum of a maximum amount of the surfactant associating with the lipid and a maximum amount of the surfactant associating with the membrane protein. A biochip wherein the above-described proteoliposome is spread on a substrate. A method for producing a proteoliposome by removing a surfactant from a mixed solution including lipid, membrane proteins and the surfactant, wherein the content of the surfactant in the mixed solution is made equal to or more than the sum of a maximum amount of the surfactant associating with the lipid and a maximum amount of the surfactant associating with the membrane protein.

Abstract: A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element, and a two-terminal switching element. The first resistive memory element is electrically coupled to the second resistive memory element and to the switching element at a common node.

Abstract: A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a break for vias first on impedance or a second on impedance to the or dummies resistive memory element in response to a control signal.

Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.

Abstract: Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.