Patents by Inventor Chandra Srivastava

Chandra Srivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10026087
    Abstract: A method for providing first data and second data for an interaction is disclosed. The first data is beneficial to a first party and necessary for the interaction, while the second data is beneficial to a second party and is not necessary for the interaction. The first data and second data are provided by a first party device in a single data element. A second party device receives the single data element, separates the first data and second data, and processes the first data and second data separately.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: July 17, 2018
    Assignee: VISA INTERNATIONAL SERVICE ASSOCIATION
    Inventors: Diane Salmon, Chandra Srivastava
  • Publication number: 20180181952
    Abstract: Disclosed is a system, process and protocol for communicating between a vehicle and an additional communication device using a variety of communication forms.
    Type: Application
    Filed: June 30, 2016
    Publication date: June 28, 2018
    Applicant: VISA International Service Association
    Inventors: Martin Enriquez, Chandra Srivastava
  • Publication number: 20180089656
    Abstract: A computer-implemented method of communicating with a point of sale terminal. The method includes establishing wireless communication with a point of sale terminal using a first communication channel, and establishing communication with the point of sale terminal using a second communication channel. The method also includes transmitting a first section of communication data via the first communication channel; and transmitting a second section of the communication data using the second communication channel.
    Type: Application
    Filed: March 31, 2016
    Publication date: March 29, 2018
    Inventors: Christopher Jones, Sanjeev Sharma, Christian Flurscheim, Chandra Srivastava, Vishwanath Shastry, Kiushan Pirzadeh, Christian Aabye
  • Publication number: 20180075455
    Abstract: A method for utilizing a non-transactable account identifier with a payment token is disclosed. The non-transactable account identifier can have the same format as a primary account number (PAN) and the payment token, but is not used to conduct a payment transaction.
    Type: Application
    Filed: November 16, 2017
    Publication date: March 15, 2018
    Inventors: Phillip Kumnick, Joseph Bjorn Ovick, Chandra Srivastava
  • Patent number: 9898568
    Abstract: Systems, apparatuses, and methods for reducing the load on the bitlines of a ROM bitcell array are described. The connections between nets of a ROM bitcell array may be assigned based on their programmed values using a traditional approach. Then, a plurality of optimizations may be performed on the assignment of nets to reduce the load on the bitlines of the array. A first optimization may swap the connections between ground and bitline for the nets of a given column responsive to detecting that the number of connections to the corresponding bitline is greater than the number of connections to ground for the given column. A second optimization may remove the connection of a net to a bitline if three consecutive nets of a given column are connected to the bitline.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: February 20, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Naveen Chandra Srivastava, Janardhan Achanta, Pankaj Kumar, Shreekanth Karandoor Sampigethaya
  • Patent number: 9846878
    Abstract: A method for utilizing a non-transactable account identifier with a payment token is disclosed. The non-transactable account identifier can have the same format as a primary account number (PAN) and the payment token, but is not used to conduct a payment transaction.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: December 19, 2017
    Assignee: Visa International Service Association
    Inventors: Phillip Kumnick, Joseph Bjorn Ovick, Chandra Srivastava
  • Patent number: 9710589
    Abstract: Systems, apparatuses, and methods for reducing the area of a semiconductor structure. A spacing violation may be detected for a gap width used to separate first and second regions of a layer of semiconductor material. In response to detecting the violation, the first and second regions are merged into a combined region, and then a cut mask layer is formed above the combined region. Next, an etch process is performed through the cut mask layer to remove an exposed third region within the combined region, wherein the exposed third region is interposed between first and second region portions of the combined region.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: July 18, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kalpeshkumar Girishchandra Dave, Naveen Chandra Srivastava, Pankaj Kumar, Janardhan Achanta, Shreekanth Karandoor Sampigethaya
  • Patent number: 9705481
    Abstract: An integrated circuit device having a p-well plane, a plurality of substantially parallel n-well rows, and a logic cell. The p-well plane is comprised of p-type semiconductor material. Each n-well row comprises an n-type layer disposed on the surface of the p-well plane. The plurality of n-well rows includes a first n-well row and a second n-well row. The logic cell is arranged on the p-well plane and the footprint of the logic cell encompasses both the first and second n-well rows.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: July 11, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sudesh Chandra Srivastava, Vivek Singhal
  • Publication number: 20170194949
    Abstract: An integrated circuit device having a p-well plane, a plurality of substantially parallel n-well rows, and a logic cell. The p-well plane is comprised of p-type semiconductor material. Each n-well row comprises an n-type layer disposed on the surface of the p-well plane. The plurality of n-well rows includes a first n-well row and a second n-well row. The logic cell is arranged on the p-well plane and the footprint of the logic cell encompasses both the first and second n-well rows.
    Type: Application
    Filed: December 31, 2015
    Publication date: July 6, 2017
    Inventors: Sudesh Chandra Srivastava, Vivek Singhal
  • Patent number: 9617159
    Abstract: The present invention relates to synthesizing reduced graphene oxide on the surface of a metal sheet and glass. The invention particularly relates to a process for coating a substrate with reduced graphene oxide using seedlac as a carbon source. As per the process of the current invention, a solution of seedlac is prepared in an alcohol and the substrate is dipped in to the solution for one or more time. The substrate is then dried in air for 1-10 minutes and thereafter, heated to a temperature range of 400 to 1200° C. under controlled atmosphere of Ar/N2/Ar—H2/N2—H2 at a different flow rate ranging from 100 to 500 seem for a period of 10 to 120 minutes.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: April 11, 2017
    Assignees: Council of Scientific and Industrial Research, Tata Steel Limited
    Inventors: Kumar Choudhary Shyam, Kumar Bhadu Manish, Kumar Rout Tapan, Das Sumitesh, Kumar Sahu Ranjan, Narayan Singhbabu Yashabanta, Kumar Pramanick Ashit, Chandra Srivastava Vikas
  • Publication number: 20170017925
    Abstract: A method is provided that includes: receiving information for a posting from a user associated with a local location and a regional location, the posting information including a location context; creating a posting, using the posting information; and making the posting viewable by members that have a location context that matches the location context determined for the posting. The method can include allowing other members to respond to the posting of the user if the other members match the location context determined for the posting. The method can also include making a connection between one of the members and the user and notifying the member of the posting by the user. The method can also include notifying a moderator of the posting and only making the posting viewable by members that have a location context that matches the location context determined for the posting if the moderator approves the posting.
    Type: Application
    Filed: July 18, 2016
    Publication date: January 19, 2017
    Inventor: YOGESH CHANDRA SRIVASTAVA
  • Publication number: 20160378898
    Abstract: Systems, apparatuses, and methods for reducing the load on the bitlines of a ROM bitcell array are described. The connections between nets of a ROM bitcell array may be assigned based on their programmed values using a traditional approach. Then, a plurality of optimizations may be performed on the assignment of nets to reduce the load on the bitlines of the array. A first optimization may swap the connections between ground and bitline for the nets of a given column responsive to detecting that the number of connections to the corresponding bitline is greater than the number of connections to ground for the given column. A second optimization may remove the connection of a net to a bitline if three consecutive nets of a given column are connected to the bitline.
    Type: Application
    Filed: June 23, 2015
    Publication date: December 29, 2016
    Inventors: Naveen Chandra Srivastava, Janardhan Achanta, Pankaj Kumar, Shreekanth Karandoor Sampigethaya
  • Publication number: 20160378899
    Abstract: Systems, apparatuses, and methods for reducing the area of a semiconductor structure. A spacing violation may be detected for a gap width used to separate first and second regions of a layer of semiconductor material. In response to detecting the violation, the first and second regions are merged into a combined region, and then a cut mask layer is formed above the combined region. Next, an etch process is performed through the cut mask layer to remove an exposed third region within the combined region, wherein the exposed third region is interposed between first and second region portions of the combined region.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 29, 2016
    Inventors: Kalpeshkumar Girishchandra Dave, Naveen Chandra Srivastava, Pankaj Kumar, Janardhan Achanta, Shreekanth Karandoor Sampigethaya
  • Publication number: 20160185604
    Abstract: The present invention relates to synthesizing reduced graphene oxide on the surface of a metal sheet and glass. The invention particularly relates to a process for coating a substrate with reduced graphene oxide using seedlac as a carbon source. As per the process of the current invention, a solution of seedlac is prepared in an alcohol and the substrate is dipped in to the solution for one or more time. The substrate is then dried in air for 1-10 minutes and thereafter, heated to a temperature range of 400 to 1200° C. under controlled atmosphere of Ar/N2/Ar—H2/N2—H2 at a different flow rate ranging from 100 to 500 seem for a period of 10 to 120 minutes.
    Type: Application
    Filed: May 8, 2014
    Publication date: June 30, 2016
    Inventors: Kumar Choudhary Shyam, Kumar Bhadu Manish, Kumar Rout Tapan, Das Sumitesh, Kumar Sahu Ranjan, Narayan Singhbabu Yashabanta, Kumar Pramanick Ashit, Chandra Srivastava Vikas
  • Publication number: 20160125458
    Abstract: A method for enabling a value-added transaction involving a vehicle and a merchant via a mobile device is disclosed. Merchant information may be broadcasted from a merchant terminal. Vehicle specific data may be received at the merchant terminal identifying the vehicle in response to the broadcasted merchant information. Transaction data may be provided to the mobile device to initiate an intended transaction. Payment data may be received from the mobile device at the merchant terminal in response to the provided transaction data. Before completing the intended transaction, a value-added transaction offer may be provided to the mobile device. In response to the provided value-added transaction offer, an acceptance of the value-added transaction offer may be received. The intended transaction and the value-added transaction offer may be completed as a single transaction.
    Type: Application
    Filed: November 5, 2015
    Publication date: May 5, 2016
    Inventors: MARTIN ENRIQUEZ, Chandra Srivastava, Joseph Bjorn Ovick
  • Patent number: 9319045
    Abstract: A circuit for reducing gate leakage current in a switchable power domain of a CMOS (complementary metal oxide semiconductor) integrated circuit chip includes a first transistor having a drain electrode coupled to a first terminal of a power switch having a second terminal coupled to a first reference voltage, the first transistor having a gate electrode, a body electrode, and a source electrode. The source electrode and body electrodes are coupled to a second reference voltage. The first transistor has a relatively high first gate leakage current that flows from its gate electrode to its body electrode if the power switch is open and a voltage of the gate electrode of the first transistor representing a first logic level exceeds a voltage of the body electrode by more than a first predetermined amount.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: April 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sudesh Chandra Srivastava, Vivek Singhal
  • Publication number: 20150287037
    Abstract: A method for providing first data and second data for an interaction is disclosed. The first data is beneficial to a first party and necessary for the interaction, while the second data is beneficial to a second party and is not necessary for the interaction. The first data and second data are provided by a first party device in a single data element. A second party device receives the single data element, separates the first data and second data, and processes the first data and second data separately.
    Type: Application
    Filed: April 7, 2015
    Publication date: October 8, 2015
    Inventors: Diane Salmon, Chandra Srivastava
  • Publication number: 20150199689
    Abstract: A method for utilizing a non-transactable account identifier with a payment token is disclosed. The non-transactable account identifier can have the same format as a primary account number (PAN) and the payment token, but is not used to conduct a payment transaction.
    Type: Application
    Filed: January 14, 2015
    Publication date: July 16, 2015
    Inventors: Phillip Kumnick, Joseph Bjorn Ovick, Chandra Srivastava
  • Publication number: 20150025229
    Abstract: The present invention provides a process and System for Separation of biomass components into individual components such as cellulose, hemicellulose and lignin. The present invention provides a process for separating lignin in its native form. The cellulose obtained by the process of the present invention is highly reactive for saccharification.
    Type: Application
    Filed: February 18, 2014
    Publication date: January 22, 2015
    Applicant: NAGARJUNA ENERGY PRIVATE LIMITED
    Inventors: Dinakaran Samuel SUDHAKARAN, Suresh Chandra SRIVASTAVA, Manoj Kumar SARKAR, Banibrata PANDEY, Sakthi Priya PECHIMUTHU
  • Patent number: 8618279
    Abstract: The invention provides a novel method for the chemical synthesis of 2?,3?-cyclic phosphate and phosphorothioate of mono and terminated oligonucleotides synthesis. The invention also provides a novel method of for the chemical synthesis of 2?,3?- and 3?,5?-cyclic phosphate and phosphorothioate mononucleotide nucleotides. The process is based on quick and efficient cyclization of phosphoramidate moiety and neighboring hydroxyl group. The present invention is directed towards the synthesis of high purity DNA and RNAs, specifically to introduce cyclic phosphate at 3?-end of oligonucleotides. Such DNA and RNA's have extensive application in therapeutics, diagnostics, drug design, and selective inhibition of an RNA sequence within cellular environment, in pre-tRNA cleavage and in ribozyme ligation. The 2?,3?-cyclic phosphate nucleosides are involved in a vast number of applications in molecular biology in general and mammalian cells in particular.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: December 31, 2013
    Assignee: ChemGenes Corporation
    Inventors: Andrei Laikhter, Suresh Chandra Srivastava, Naveen Srivastava