Patents by Inventor Chandra Tiwari

Chandra Tiwari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12279431
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: April 15, 2025
    Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
  • Publication number: 20250085344
    Abstract: Aspects of the subject disclosure may include, for example, monitoring first data to identify a first plurality of test points, analyzing the first plurality of test points to identify the first data as being associated with a first time domain included in a plurality of time domains, wherein respective portions of a device under test (DUT) are operative in accordance with a given time domain included in the plurality of time domains, and based on the analyzing of the first plurality of test points, generating first control signals to cause a first clock signal to be adapted to generate a second clock signal that is different from the first clock signal.
    Type: Application
    Filed: November 1, 2023
    Publication date: March 13, 2025
    Applicant: NXP B.V.
    Inventors: CHANDAN GUPTA, SATISH CHANDRA TIWARI, ABHISHEK ASHOK BAJPAEE
  • Patent number: 12063783
    Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: March 3, 2023
    Date of Patent: August 13, 2024
    Inventors: Xiaosong Zhang, Yi Hu, Tom J. John, Wei Yeeng Ng, Chandra Tiwari
  • Publication number: 20240071932
    Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stack in the stair-step region comprises a cavity comprising a flight of stairs in a vertical cross-section along a first direction. The first tiers are conductive and the second tiers are insulative in a finished-circuitry construction. An insulating lining is formed in the cavity atop treads of the stairs and laterally-over sidewalls of the cavity that are along the first direction. Individual of the treads comprise conducting material of one of the conductive tiers in the finished-circuitry construction. The insulating lining is thicker in a bottom part of the cavity than over the sidewalls of the cavity that are above the bottom part. Insulative material is formed in the cavity directly above the insulating lining. Conductive vias are formed through the insulative material and the insulating lining.
    Type: Application
    Filed: September 14, 2022
    Publication date: February 29, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Jivaan Kishore Jhothiraman, Chandra Tiwari
  • Publication number: 20240047346
    Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs. A lining has a specific resistance of at least 1×104 ohm·m at 20° C. atop treads of the stairs of the flight of stairs. Individual of the treads comprise conducting material of one of the conductive tiers. The lining comprises at least one of (a), (b), (c), and (d), where: (a): M1xM2yOz having a specific resistance of at least 1×104 ohm·m at 20° C.
    Type: Application
    Filed: August 3, 2022
    Publication date: February 8, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Rutuparna Narulkar, Chandra Tiwari, Dmitry Mikulik, Erica A. Ellingson, Yucheng Wang, Mathew Thomas
  • Patent number: 11893064
    Abstract: Different logical partitions representing parts of a distributed file system global namespace are hosted on some cluster nodes, e.g., metadata nodes. File content and shadow logical partitions corresponding to the different logical partitions are hosted on other nodes, e.g., data nodes. Each file is associated with a metadata and data node. TCP links are established between nodes. Upon opening files, a file manager server session is generated between each pair of nodes associated with the open files to track open states and is recorded in a mapping table. The mapping table identifies each open file and associated nodes. When a metadata or data node of a particular pair of nodes associated with an open file becomes unavailable, the mapping table is consulted to identify another of the metadata or data node associated with the open file. Crash recovery protocols are performed on the other of the metadata or data node.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: February 6, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Vishal Chandra Tiwary, Xiaobing Zhang, Abhishek Rajimwale
  • Publication number: 20230292510
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: May 17, 2023
    Publication date: September 14, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
  • Patent number: 11706924
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
  • Patent number: 11700729
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
  • Publication number: 20230209827
    Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.
    Type: Application
    Filed: March 3, 2023
    Publication date: June 29, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Xiaosong Zhang, Yi Hu, Tom J. John, Wei Yeeng Ng, Chandra Tiwari
  • Patent number: 11626423
    Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: April 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Xiaosong Zhang, Yi Hu, Tom J. John, Wei Yeeng Ng, Chandra Tiwari
  • Patent number: 11444093
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. A horizontal pattern of operative memory-cell pillars extends through the insulative tiers and the conductive tiers in individual of the memory blocks. The operative memory-cell pillars have intrinsic compressive mechanical stress. At least one dummy structure in the individual memory blocks extends through at least upper of the insulative tiers and the conductive tiers. The at least one dummy structure is at least one of (a) and (b), where (a): at a lateral edge of the horizontal pattern, and (b): at a longitudinal end of the horizontal pattern. The at least one dummy structure has intrinsic tensile mechanical stress. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Tiwari
  • Publication number: 20220238553
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: April 12, 2022
    Publication date: July 28, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunai Shrotri, Swapnil Lengade
  • Patent number: 11329064
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
  • Patent number: 11302712
    Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. At least a portion of sidewalls of the cavity is lined with sacrificial material. Insulative material is formed in the cavity radially inward of the sacrificial material. At least some of the sacrificial material is removed from being between the cavity sidewalls and the insulative material to form a void space there-between. Insulator material is formed in at least some of the void space. Other embodiments, including structure independent of method, are disclosed.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chandra Tiwari, Jivaan Kishore Jhothiraman
  • Publication number: 20220077169
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.
    Type: Application
    Filed: November 12, 2021
    Publication date: March 10, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
  • Patent number: 11205654
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
  • Publication number: 20210391352
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: June 16, 2020
    Publication date: December 16, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Ramey M. Abdelrahaman, Jeslin J. Wu, Chandra Tiwari, Kunal Shrotri, Swapnil Lengade
  • Publication number: 20210335803
    Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. At least a portion of sidewalls of the cavity is lined with sacrificial material. Insulative material is formed in the cavity radially inward of the sacrificial material. At least some of the sacrificial material is removed from being between the cavity sidewalls and the insulative material to form a void space there-between. Insulator material is formed in at least some of the void space. Other embodiments, including structure independent of method, are disclosed.
    Type: Application
    Filed: April 23, 2020
    Publication date: October 28, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Chandra Tiwari, Jivaan Kishore Jhothiraman
  • Publication number: 20210240768
    Abstract: Different logical partitions representing parts of a distributed file system global namespace are hosted on some cluster nodes, e.g., metadata nodes. File content and shadow logical partitions corresponding to the different logical partitions are hosted on other nodes, e.g., data nodes. Each file is associated with a metadata and data node. TCP links are established between nodes. Upon opening files, a file manager server session is generated between each pair of nodes associated with the open files to track open states and is recorded in a mapping table. The mapping table identifies each open file and associated nodes. When a metadata or data node of a particular pair of nodes associated with an open file becomes unavailable, the mapping table is consulted to identify another of the metadata or data node associated with the open file. Crash recovery protocols are performed on the other of the metadata or data node.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 5, 2021
    Inventors: Vishal Chandra Tiwary, Xiaobing Zhang, Abhishek Rajimwale