Patents by Inventor Chandrabhan Kushwah

Chandrabhan Kushwah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • 8T BASED SRAM CELL AND RELATED METHOD
    Publication number: 20150325286
    Abstract: Various embodiments include memory devices and related methods. An embodiment includes circuitry including: a first inverter having a first inverter storage node, the first inverter cross-coupled to a second inverter having a second inverter storage node, wherein each of the first inverter and the second inverter has a reverse bit line controlled feedback transistor coupled between an pull-down transistor and a pull-up transistor, and wherein each pull-down transistor is further coupled to a ground; a first signal line coupled with the reverse bit line controlled feedback transistor of the second inverter; a second signal line coupled with the reverse bit line controlled feedback transistor of the first inverter; a first access transistor coupled with the first inverter storage node, the first signal line, and a third signal line; and a second access transistor coupled with the second inverter storage node, the second signal line, and the third signal line.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 12, 2015
    Applicant: International Business Machines Corporation
    Inventors: Devesh Dwivedi, Chandrabhan Kushwah, Sathisha Nanjundegowda
  • 8T based SRAM cell and related method
    Patent number: 9177636
    Abstract: Various embodiments include memory devices and related methods. An embodiment includes circuitry including: a first inverter having a first inverter storage node, the first inverter cross-coupled to a second inverter having a second inverter storage node, wherein each of the first inverter and the second inverter has a reverse bit line controlled feedback transistor coupled between an pull-down transistor and a pull-up transistor, and wherein each pull-down transistor is further coupled to a ground; a first signal line coupled with the reverse bit line controlled feedback transistor of the second inverter; a second signal line coupled with the reverse bit line controlled feedback transistor of the first inverter; a first access transistor coupled with the first inverter storage node, the first signal line, and a third signal line; and a second access transistor coupled with the second inverter storage node, the second signal line, and the third signal line.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: November 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Devesh Dwivedi, Chandrabhan Kushwah, Sathisha Nanjundegowda