Patents by Inventor Chandrahas Tirumulasetty

Chandrahas Tirumulasetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods, systems, and computer readable media for performing page fault handling
    Patent number: 11474952
    Abstract: Methods, systems, and computer readable media for performing page fault handling are disclosed. According to one method, the method includes: after a translation lookaside buffer (TLB) miss associated with a virtual memory page occurs, identifying, in a page table, a page table entry (PTE) associated with the virtual memory page; determining, using a first indicator in the PTE, that the virtual memory page is not present in a main memory; determining, using a second indicator in the PTE, that the virtual memory page is associated with a valid memory address and that the virtual memory page is capable of using pre-allocated pages; obtaining, from a pre-allocation table, a page frame number associated with a pre-allocated page; and updating the PTE to indicate the page frame number.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: October 18, 2022
    Assignees: The Texas A&M University System, Hewlett Packard Enterprise Development LP
    Inventors: Narasimha Reddy Annapareddy, Chih-Chieh Chou, Chandrahas Tirumulasetty, Paul Gratz, Ayman Abouelwafa
  • METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR PERFORMING PAGE FAULT HANDLING
    Publication number: 20210374071
    Abstract: Methods, systems, and computer readable media for performing page fault handling are disclosed. According to one method, the method includes: after a translation lookaside buffer (TLB) miss associated with a virtual memory page occurs, identifying, in a page table, a page table entry (PTE) associated with the virtual memory page; determining, using a first indicator in the PTE, that the virtual memory page is not present in a main memory; determining, using a second indicator in the PTE, that the virtual memory page is associated with a valid memory address and that the virtual memory page is capable of using pre-allocated pages; obtaining, from a pre-allocation table, a page frame number associated with a pre-allocated page; and updating the PTE to indicate the page frame number.
    Type: Application
    Filed: June 1, 2021
    Publication date: December 2, 2021
    Inventors: Narasimha Reddy Annapareddy, Chih-Chieh Chou, Chandrahas Tirumulasetty, Paul Gratz, Ayman Abouelwafa