Abstract: An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

Abstract: An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners.

Abstract: An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners.

Abstract: An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners.

Abstract: An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners.

Abstract: In accordance with an embodiment, a method of performing a successive approximation analog-to-digital (A/D) conversion includes determining a voltage range of an analog input voltage in a single cycle using a multi-bit flash A/D converter, determining an initial D/A value for a successive approximation based on determining the voltage range, and successively approximating the analog input voltage. Successively approximating includes providing the initial D/A value to a D/A converter, comparing an output of the D/A converter with the analog input voltage, and determining a further D/A value based on the comparing.

Abstract: A multiplying digital-to-analog converter suited to maintain impedance balancing during phases. In an embodiment, an input signal may be sampled onto nodes of impedance elements during an initial phase. In a second phase the impedance elements are directly coupled either to a non-inverting reference input or the inverting reference input of an amplifier depending on an output of a related flash ADC output. The determination as to which capacitor is to be coupled to inverting or non-inverting input nodes may be directly programmed into the MDAC using switches, such that a thermometric to binary converter is not required in an example embodiment. Thus, the number of impedance elements coupled to the non-inverting reference input or inverting reference input REFM remains constant in each cycle such that there is no need to settle the non-inverting reference input or inverting reference input to full accuracy.

Abstract: An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values.

Abstract: In accordance with an embodiment, a method of performing a successive approximation analog-to-digital (A/D) conversion includes determining a voltage range of an analog input voltage in a single cycle using a multi-bit flash A/D converter, determining an initial D/A value for a successive approximation based on determining the voltage range, and successively approximating the analog input voltage. Successively approximating includes providing the initial D/A value to a D/A converter, comparing an output of the D/A converter with the analog input voltage, and determining a further D/A value based on the comparing.

Abstract: An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values.

Abstract: An embodiment of a multiplying digital-to-analog converter (MDAC), an embodiment of a method for converting a digital signal to an analog signal, an embodiment of a pipelined analog-to-digital converter (ADC), and a method of converting an analog signal to a digital signal in a plurality of cascading stages.

Abstract: A switched charge storage element integrator in a continuous or discrete time circuit, the integrator including a differential input amplifier, a first 2-terminal charge storage element, a second 2-terminal charge storage element, and a plurality of controlled switches. The differential input amplifier is coupled to a capacitor and a resistor and configured as an inverting integrator. An inverting terminal of the amplifier is coupled to two controlled switches. A non-inverting terminal of the amplifier is coupled to a reference voltage. The first and second switched charge storage element blocks are alternatingly coupled to the inverting terminal INM of the amplifier XOPA during the active state of a second clock signal and a first clock signal, respectively, for making the supply noise continuous and eliminating its dependency on the clock phases, thereby zeroing its convolution with the clock signal.

Abstract: Techniques for operating a switched-capacitor circuit to reduce input and feedback dependence and/or reduce reference modulation. A switched-capacitor circuit can be operated in four phases. In a first phase at a start of a cycle, the capacitor is charged/discharged by a common mode signal to mask any residual charge stored in the capacitor from a previous cycle. In a second phase, the capacitor is charged with an input signal. During a third phase, the capacitor is charged with a wide-bandwidth auxiliary reference signal, and during a fourth phase the capacitor is charged with a reference signal. During the third and fourth phases, the capacitor may be coupled to an integrating circuit to integrate a difference between the input signal and the reference signal.

Abstract: The present disclosure relates to reduction in the effect of kickback in comparators by means of charge injection implemented by means of voltage controlled switches with attributes similar to those of an input differential pair. The voltage controlled switches produce charge to neutralize the charge loss during latching of inputs in the comparator.

Abstract: The present disclosure relates to reduction in the effect of kickback in comparators by means of charge injection implemented by means of voltage controlled switches with attributes similar to those of an input differential pair. The voltage controlled switches produce charge to neutralize the charge loss during latching of inputs in the comparator.

Abstract: Techniques for operating a switched-capacitor circuit to reduce input and feedback dependence and/or reduce reference modulation. A switched-capacitor circuit can be operated in four phases. In a first phase at a start of a cycle, the capacitor is charged/discharged by a common mode signal to mask any residual charge stored in the capacitor from a previous cycle. In a second phase, the capacitor is charged with an input signal. During a third phase, the capacitor is charged with a wide-bandwidth auxiliary reference signal, and during a fourth phase the capacitor is charged with a reference signal. During the third and fourth phases, the capacitor may be coupled to an integrating to circuit to integrate a difference between the input signal and the reference signal.

Abstract: An adaptive biasing technique improves fully differential gain boosted operational amplifiers transient characteristics and reduces power consumption. An adaptive biasing module includes a bias generation module and a bias replication module. The bias generation module generates a first control signal (VCMNB) and the first control signal is applied as an output common mode of a differential booster (inside the bias replication module). The bias replication module is coupled to the bias generation module for equalizing a common mode of the differential booster with the first control signal (VCMNB).

Abstract: Embodiments of the present invention disclose operational amplifiers which demonstrate good settling behavior with minimum over-shoot or ringing for improving settling behavior. The amplifiers include one or more amplification stages connected to form a symmetric structure. The amplification stage includes a boosting amplifier, a MOS transistor and a compensation capacitor. The MOS transistor can be an NMOS transistor and a PMOS transistor. Using this scheme pole-zero doublets are rearranged in a manner to improve the transient settling response.

Abstract: A switched charge storage element integrator in a continuous or discrete time circuit, the integrator including a differential input amplifier, a first 2-terminal charge storage element, a second 2-terminal charge storage element, and a plurality of controlled switches. The differential input amplifier is coupled to a capacitor and a resistor and configured as an inverting integrator. An inverting terminal of the amplifier is coupled to two controlled switches. A non-inverting terminal of the amplifier is coupled to a reference voltage. The first and second switched charge storage element blocks are alternatingly coupled to the inverting terminal INM of the amplifier XOPA during the active state of a second clock signal and a first clock signal, respectively, for making the supply noise continuous and eliminating its dependency on the clock phases, thereby zeroing its convolution with the clock signal.

Abstract: A continuous time common mode feedback module is capable of operating in a wide range of input voltages. The common mode feedback module includes a common mode detector and an amplifier for computing and amplifying the difference of a reference voltage and a common mode voltage of a first input signal and a second input signal. The common-mode feedback module includes a common mode resolver and a control voltage generating module coupled to each other to provide a common mode feedback voltage. The common mode feedback module provides a good linearity and a wide bandwidth, without compensation requirements. The common mode feedback module also provides small process corner dependence of bias current and a common mode offset.