Patents by Inventor Chandrakant Patadia

Chandrakant Patadia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040087047
    Abstract: A method for processing a partially fabricated semiconductor wafer having a layer of nichrome resistor material patterned to form a plurality of nichrome resistors on a surface of the wafer includes performing a wet pre-metallization cleaning step on the wafer surface, performing an RF argon plasma sputter etching process on the wafer surface, advancing the wafer into a second reactor without breaking a vacuum in either reactor, depositing a layer of metal on the surface, patterning the metal to form a predetermined metal interconnection pattern thereof, performing a stabilization bake cycles on the wafer, measuring the TCR of the nichrome resistor material, and rejecting the wafer if the measured TCR is greater than a predetermined value.
    Type: Application
    Filed: October 6, 2003
    Publication date: May 6, 2004
    Inventors: Rajneesh Jaiswal, Chandrakant Patadia
  • Patent number: 6664166
    Abstract: A method for processing a partially fabricated semiconductor wafer having a layer of nichrome resistor material patterned to form a plurality of nichrome resistors on a surface of the wafer includes performing a wet pre-metallization cleaning step on the wafer surface, performing an RF argon plasma sputter etching process on the wafer surface, advancing the wafer into a second reactor without breaking a vacuum in either reactor, depositing a layer of metal on the surface, patterning the metal to form a predetermined metal interconnection pattern thereof, performing a stabilization bake cycles on the wafer, measuring the TCR of the nichrome resistor material, and rejecting the wafer if the measured TCR is greater than a predetermined value.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: December 16, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Rajneesh Jaiswal, Chandrakant Patadia